From patchwork Fri Jan 16 17:30:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 5649771 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 35725C058D for ; Fri, 16 Jan 2015 17:31:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 19701202F2 for ; Fri, 16 Jan 2015 17:31:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DAB6B2034C for ; Fri, 16 Jan 2015 17:31:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755163AbbAPRbQ (ORCPT ); Fri, 16 Jan 2015 12:31:16 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:17210 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754770AbbAPRbO (ORCPT ); Fri, 16 Jan 2015 12:31:14 -0500 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NIA00BCE600OG50@mailout4.samsung.com>; Sat, 17 Jan 2015 02:31:12 +0900 (KST) X-AuditID: cbfee61b-f79d76d0000024d6-53-54b94ae0b92a Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 73.5D.09430.0EA49B45; Sat, 17 Jan 2015 02:31:12 +0900 (KST) Received: from amdc1344.digital.local ([106.116.147.32]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NIA001ES5Z9UMA0@mmp2.samsung.com>; Sat, 17 Jan 2015 02:31:12 +0900 (KST) From: Sylwester Nawrocki To: kishon@ti.com, kgene@kernel.org Cc: devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sylwester Nawrocki , Pankaj Dubey , Kukjin Kim Subject: [PATCH 1/2] phy: exynos-video-mipi: Fix regression by adding support for PMU regmap Date: Fri, 16 Jan 2015 18:30:37 +0100 Message-id: <1421429438-32090-1-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgluLIzCtJLcpLzFFi42I5/e+xoO4Dr50hBrMPyVvMP3KO1aJ3wVU2 i/7Hr5ktLjztYbPY9Pgaq8WM8/uYLBZt/cJucfhNO6sDh8emVZ1sHpuX1Hv0bVnF6HH8xnYm j8+b5AJYo7hsUlJzMstSi/TtErgyju24zVLw1qZi7sZGlgbG6UZdjJwcEgImEg/aLrJA2GIS F+6tZ+ti5OIQEpjOKNEwvY8dwulgkpi5Zjc7SBWbgKFE79E+RhBbREBZYmFXLzNIEbPAc0aJ l3e7mEASwgJxEg+fPgEbyyKgKrFk0iSwZl4BN4mdva9Yuxg5gNYpSMyZZDOBkXsBI8MqRtHU guSC4qT0XCO94sTc4tK8dL3k/NxNjOBweSa9g3FVg8UhRgEORiUe3hlbdoQIsSaWFVfmHmKU 4GBWEuGttdoZIsSbklhZlVqUH19UmpNafIhRmoNFSZxXyb4tREggPbEkNTs1tSC1CCbLxMEp 1cDYWrMh4dKKVSVhamv+prg89o8ofVmUnbHDaELKlZtHb7+e8Kd03z6/Bbu7XDh/3Gf7f09S 6WRw6LOlbJ9f7J5SInjx5IdP/lu3+7d7ek7Y1jdB7dFUpz++2UXbc7prPLT1+vLTTqWuPyiU yTbxvnefjsWZy7OStlipuLqZ5uZYxV8QEnPYoLpSiaU4I9FQi7moOBEAXZ5AWRMCAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP After the Exynos Power Management Unit (PMU) driver was converted to the platform device driver in commit 14fc8b93d47323561edf5d482 ("ARM: EXYNOS: Add platform driver support for Exynos PMU") and then PMU device nodes added to Exynos4 DTs in commit 7b9613aca42a5522d269 ("ARM: dts: add PMU syscon node for exynos4") the mipi video phy driver started failing probing, due to overlapping memory mapped register region resources. Now all the Exynos peripheral devices which have registers in the PMU region are supposed to use the regmap provided by the syscon driver. So support for regmap is added in this patch, this unfortunately creates yet another indirection into that supposedly trivial driver. The additional mutex is required because single register is used by PHY pairs (they share bit in a register). An improvement here could be to allow a PHY instance be created with a driver custom mutex, which would then be common for each PHY pair. This would eliminate one of 3 mutexes which need to be taken in the phy_power_on/ phy_power_off code path. However, I tried to keep this bug fix patch possibly simple. This change is needed to make MIPI DSI displays and MIPI CSI-2 camera sensors working again on Exynos4 boards. Cc: Pankaj Dubey Cc: Kukjin Kim Signed-off-by: Sylwester Nawrocki --- .../devicetree/bindings/phy/samsung-phy.txt | 2 +- drivers/phy/phy-exynos-mipi-video.c | 89 +++++++++++++------- include/linux/mfd/syscon/exynos4-pmu.h | 21 +++++ 3 files changed, 79 insertions(+), 33 deletions(-) create mode 100644 include/linux/mfd/syscon/exynos4-pmu.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index d5bad92..91e38cf 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -3,8 +3,8 @@ Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY Required properties: - compatible : should be "samsung,s5pv210-mipi-video-phy"; -- reg : offset and length of the MIPI DPHY register set; - #phy-cells : from the generic phy bindings, must be 1; +- syscon - phandle to the PMU system controller; For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in the PHY specifier identifies the PHY and its meaning is as follows: diff --git a/drivers/phy/phy-exynos-mipi-video.c b/drivers/phy/phy-exynos-mipi-video.c index 943e0f8..f017b2f 100644 --- a/drivers/phy/phy-exynos-mipi-video.c +++ b/drivers/phy/phy-exynos-mipi-video.c @@ -12,19 +12,18 @@ #include #include #include +#include #include #include #include #include #include +#include #include +#include -/* MIPI_PHYn_CONTROL register offset: n = 0..1 */ +/* MIPI_PHYn_CONTROL reg. offset (for base address from ioremap): n = 0..1 */ #define EXYNOS_MIPI_PHY_CONTROL(n) ((n) * 4) -#define EXYNOS_MIPI_PHY_ENABLE (1 << 0) -#define EXYNOS_MIPI_PHY_SRESETN (1 << 1) -#define EXYNOS_MIPI_PHY_MRESETN (1 << 2) -#define EXYNOS_MIPI_PHY_RESET_MASK (3 << 1) enum exynos_mipi_phy_id { EXYNOS_MIPI_PHY_ID_CSIS0, @@ -38,43 +37,62 @@ enum exynos_mipi_phy_id { ((id) == EXYNOS_MIPI_PHY_ID_DSIM0 || (id) == EXYNOS_MIPI_PHY_ID_DSIM1) struct exynos_mipi_video_phy { - spinlock_t slock; struct video_phy_desc { struct phy *phy; unsigned int index; } phys[EXYNOS_MIPI_PHYS_NUM]; + spinlock_t slock; void __iomem *regs; + struct mutex mutex; + struct regmap *regmap; }; static int __set_phy_state(struct exynos_mipi_video_phy *state, enum exynos_mipi_phy_id id, unsigned int on) { + const unsigned int offset = EXYNOS4_MIPI_PHY_CONTROL(id / 2); void __iomem *addr; - u32 reg, reset; - - addr = state->regs + EXYNOS_MIPI_PHY_CONTROL(id / 2); + u32 val, reset; if (is_mipi_dsim_phy_id(id)) - reset = EXYNOS_MIPI_PHY_MRESETN; - else - reset = EXYNOS_MIPI_PHY_SRESETN; - - spin_lock(&state->slock); - reg = readl(addr); - if (on) - reg |= reset; + reset = EXYNOS4_MIPI_PHY_MRESETN; else - reg &= ~reset; - writel(reg, addr); - - /* Clear ENABLE bit only if MRESETN, SRESETN bits are not set. */ - if (on) - reg |= EXYNOS_MIPI_PHY_ENABLE; - else if (!(reg & EXYNOS_MIPI_PHY_RESET_MASK)) - reg &= ~EXYNOS_MIPI_PHY_ENABLE; + reset = EXYNOS4_MIPI_PHY_SRESETN; + + if (state->regmap) { + mutex_lock(&state->mutex); + regmap_read(state->regmap, offset, &val); + if (on) + val |= reset; + else + val &= ~reset; + regmap_write(state->regmap, offset, val); + if (on) + val |= EXYNOS4_MIPI_PHY_ENABLE; + else if (!(val & EXYNOS4_MIPI_PHY_RESET_MASK)) + val &= ~EXYNOS4_MIPI_PHY_ENABLE; + regmap_write(state->regmap, offset, val); + mutex_unlock(&state->mutex); + } else { + addr = state->regs + EXYNOS_MIPI_PHY_CONTROL(id / 2); + + spin_lock(&state->slock); + val = readl(addr); + if (on) + val |= reset; + else + val &= ~reset; + writel(val, addr); + /* Clear ENABLE bit only if MRESETN, SRESETN bits are not set */ + if (on) + val |= EXYNOS4_MIPI_PHY_ENABLE; + else if (!(val & EXYNOS4_MIPI_PHY_RESET_MASK)) + val &= ~EXYNOS4_MIPI_PHY_ENABLE; + + writel(val, addr); + spin_unlock(&state->slock); + } - writel(reg, addr); - spin_unlock(&state->slock); return 0; } @@ -118,7 +136,6 @@ static int exynos_mipi_video_phy_probe(struct platform_device *pdev) { struct exynos_mipi_video_phy *state; struct device *dev = &pdev->dev; - struct resource *res; struct phy_provider *phy_provider; unsigned int i; @@ -126,14 +143,22 @@ static int exynos_mipi_video_phy_probe(struct platform_device *pdev) if (!state) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + state->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon"); + if (IS_ERR(state->regmap)) { + struct resource *res; - state->regs = devm_ioremap_resource(dev, res); - if (IS_ERR(state->regs)) - return PTR_ERR(state->regs); + dev_info(dev, "regmap lookup failed: %ld\n", + PTR_ERR(state->regmap)); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + state->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(state->regs)) + return PTR_ERR(state->regs); + } dev_set_drvdata(dev, state); spin_lock_init(&state->slock); + mutex_init(&state->mutex); for (i = 0; i < EXYNOS_MIPI_PHYS_NUM; i++) { struct phy *phy = devm_phy_create(dev, NULL, diff --git a/include/linux/mfd/syscon/exynos4-pmu.h b/include/linux/mfd/syscon/exynos4-pmu.h new file mode 100644 index 0000000..278b1b1 --- /dev/null +++ b/include/linux/mfd/syscon/exynos4-pmu.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _LINUX_MFD_SYSCON_PMU_EXYNOS4_H_ +#define _LINUX_MFD_SYSCON_PMU_EXYNOS4_H_ + +/* Exynos4 PMU register definitions */ + +/* MIPI_PHYn_CONTROL register offset: n = 0..1 */ +#define EXYNOS4_MIPI_PHY_CONTROL(n) (0x710 + (n) * 4) +#define EXYNOS4_MIPI_PHY_ENABLE (1 << 0) +#define EXYNOS4_MIPI_PHY_SRESETN (1 << 1) +#define EXYNOS4_MIPI_PHY_MRESETN (1 << 2) +#define EXYNOS4_MIPI_PHY_RESET_MASK (3 << 1) + +#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS4_H_ */