From patchwork Mon Feb 2 20:58:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Valentin X-Patchwork-Id: 5764071 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 44CAE9F380 for ; Mon, 2 Feb 2015 21:01:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2C9312097B for ; Mon, 2 Feb 2015 21:01:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F362820975 for ; Mon, 2 Feb 2015 21:01:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933238AbbBBVBG (ORCPT ); Mon, 2 Feb 2015 16:01:06 -0500 Received: from mail-pa0-f49.google.com ([209.85.220.49]:45465 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965159AbbBBU7Y (ORCPT ); Mon, 2 Feb 2015 15:59:24 -0500 Received: by mail-pa0-f49.google.com with SMTP id fa1so86977437pad.8; Mon, 02 Feb 2015 12:59:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IZNhXMtvvpw41jaOPveFi/smfKfZgOrK+qpXQTs7X+c=; b=JKe8a6JI2l2LlfhBT9jv2CwF0MHWLGiXgGq7GA43eZHBwCDWA7FtPW5GDMAMJs2eBG FV2bgx8d/sjAt156EbANmdRDgfK9d//Os6x2JxVskbjH6S1rlTEyyXk8aFuZbjhdz+BW sGUdfEhzORU1litnPJsVuoDNTeWiMcCzzWTygLN4JQ/Hm5Ek6ge4przBpspRFHhmOiEJ ZpcliaPXpeUAygtAmF4HtklDK8YmksfrOLMS5xJ76UL2w34RITj4oLujMm0OezAtNKXJ 6OuprGmFgcsgO4Lv1hmbT5hxX6b8sRcSKFmxEzUIKBySu49b54rhcqteg8Etq5DE3UHH TTFQ== X-Received: by 10.66.66.46 with SMTP id c14mr32312099pat.136.1422910763779; Mon, 02 Feb 2015 12:59:23 -0800 (PST) Received: from localhost (amazon.gigabitethernet4-0-6.asr1.snv2.gblx.net. [64.211.110.86]) by mx.google.com with ESMTPSA id mm9sm19628967pbc.76.2015.02.02.12.59.21 (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128/128); Mon, 02 Feb 2015 12:59:22 -0800 (PST) From: Eduardo Valentin To: Linux PM , Viresh Kumar Cc: Eduardo Valentin , "Rafael J. Wysocki" , Kukjin Kim , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/14] cpufreq: exynox-cpufreq: pass exynos_dvfs_info to .set_freq callback Date: Mon, 2 Feb 2015 16:58:13 -0400 Message-Id: <1422910697-5920-11-git-send-email-edubezval@gmail.com> X-Mailer: git-send-email 2.1.3 In-Reply-To: <1422910697-5920-1-git-send-email-edubezval@gmail.com> References: <1422910697-5920-1-git-send-email-edubezval@gmail.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This change passes the exynos_dvfs_info to the .set_freq callback to avoid using local static variables. Now, the core can use same allocated data structure and child code can work on same data structure. Cc: "Rafael J. Wysocki" Cc: Viresh Kumar Cc: Kukjin Kim Cc: linux-pm@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Eduardo Valentin --- drivers/cpufreq/exynos-cpufreq.c | 2 +- drivers/cpufreq/exynos-cpufreq.h | 2 +- drivers/cpufreq/exynos4210-cpufreq.c | 17 ++++++++++------- drivers/cpufreq/exynos4x12-cpufreq.c | 19 +++++++++++-------- drivers/cpufreq/exynos5250-cpufreq.c | 19 +++++++++++-------- 5 files changed, 34 insertions(+), 25 deletions(-) diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c index 5e98c6b..a964602 100644 --- a/drivers/cpufreq/exynos-cpufreq.c +++ b/drivers/cpufreq/exynos-cpufreq.c @@ -108,7 +108,7 @@ static int exynos_cpufreq_scale(unsigned int target_freq) } } - exynos_info->set_freq(old_index, index); + exynos_info->set_freq(exynos_info, old_index, index); /* When the new frequency is lower than current frequency */ if ((target_freq < old_freq) || diff --git a/drivers/cpufreq/exynos-cpufreq.h b/drivers/cpufreq/exynos-cpufreq.h index 9f2062a..b59558e 100644 --- a/drivers/cpufreq/exynos-cpufreq.h +++ b/drivers/cpufreq/exynos-cpufreq.h @@ -48,7 +48,7 @@ struct exynos_dvfs_info { struct clk *cpu_clk; unsigned int *volt_table; struct cpufreq_frequency_table *freq_table; - void (*set_freq)(unsigned int, unsigned int); + void (*set_freq)(struct exynos_dvfs_info *, unsigned int, unsigned int); bool (*need_apll_change)(unsigned int, unsigned int); void __iomem *cmu_regs; }; diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c index fc02a39..00889a4 100644 --- a/drivers/cpufreq/exynos4210-cpufreq.c +++ b/drivers/cpufreq/exynos4210-cpufreq.c @@ -55,7 +55,8 @@ static struct apll_freq apll_freq_4210[] = { APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3), }; -static void exynos4210_set_clkdiv(unsigned int div_index) +static void exynos4210_set_clkdiv(struct exynos_dvfs_info *cpufreq, + unsigned int div_index) { unsigned int tmp; @@ -80,7 +81,8 @@ static void exynos4210_set_clkdiv(unsigned int div_index) } while (tmp & 0x11); } -static void exynos4210_set_apll(unsigned int index) +static void exynos4210_set_apll(struct exynos_dvfs_info *cpufreq, + unsigned int index) { unsigned int tmp, freq = apll_freq_4210[index].freq; @@ -104,15 +106,16 @@ static void exynos4210_set_apll(unsigned int index) } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); } -static void exynos4210_set_frequency(unsigned int old_index, +static void exynos4210_set_frequency(struct exynos_dvfs_info *cpufreq, + unsigned int old_index, unsigned int new_index) { if (old_index > new_index) { - exynos4210_set_clkdiv(new_index); - exynos4210_set_apll(new_index); + exynos4210_set_clkdiv(cpufreq, new_index); + exynos4210_set_apll(cpufreq, new_index); } else if (old_index < new_index) { - exynos4210_set_apll(new_index); - exynos4210_set_clkdiv(new_index); + exynos4210_set_apll(cpufreq, new_index); + exynos4210_set_clkdiv(cpufreq, new_index); } } diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c index 7e0dd2a..d12087b 100644 --- a/drivers/cpufreq/exynos4x12-cpufreq.c +++ b/drivers/cpufreq/exynos4x12-cpufreq.c @@ -100,7 +100,8 @@ static struct apll_freq apll_freq_4412[] = { APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2), }; -static void exynos4x12_set_clkdiv(unsigned int div_index) +static void exynos4x12_set_clkdiv(struct exynos_dvfs_info *cpufreq, + unsigned int div_index) { unsigned int tmp; @@ -125,7 +126,8 @@ static void exynos4x12_set_clkdiv(unsigned int div_index) } while (tmp != 0x0); } -static void exynos4x12_set_apll(unsigned int index) +static void exynos4x12_set_apll(struct exynos_dvfs_info *cpufreq, + unsigned int index) { unsigned int tmp, freq = apll_freq_4x12[index].freq; @@ -151,15 +153,16 @@ static void exynos4x12_set_apll(unsigned int index) } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); } -static void exynos4x12_set_frequency(unsigned int old_index, - unsigned int new_index) +static void exynos4x12_set_frequency(struct exynos_dvfs_info *cpufreq, + unsigned int old_index, + unsigned int new_index) { if (old_index > new_index) { - exynos4x12_set_clkdiv(new_index); - exynos4x12_set_apll(new_index); + exynos4x12_set_clkdiv(cpufreq, new_index); + exynos4x12_set_apll(cpufreq, new_index); } else if (old_index < new_index) { - exynos4x12_set_apll(new_index); - exynos4x12_set_clkdiv(new_index); + exynos4x12_set_apll(cpufreq, new_index); + exynos4x12_set_clkdiv(cpufreq, new_index); } } diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c index d3ce829..191a511 100644 --- a/drivers/cpufreq/exynos5250-cpufreq.c +++ b/drivers/cpufreq/exynos5250-cpufreq.c @@ -80,7 +80,8 @@ static struct apll_freq apll_freq_5250[] = { APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2), }; -static void set_clkdiv(unsigned int div_index) +static void set_clkdiv(struct exynos_dvfs_info *cpufreq, + unsigned int div_index) { unsigned int tmp; @@ -103,7 +104,8 @@ static void set_clkdiv(unsigned int div_index) cpu_relax(); } -static void set_apll(unsigned int index) +static void set_apll(struct exynos_dvfs_info *cpufreq, + unsigned int index) { unsigned int tmp; unsigned int freq = apll_freq_5250[index].freq; @@ -130,15 +132,16 @@ static void set_apll(unsigned int index) } while (tmp != (0x1 << 16)); } -static void exynos5250_set_frequency(unsigned int old_index, - unsigned int new_index) +static void exynos5250_set_frequency(struct exynos_dvfs_info *exynos_info, + unsigned int old_index, + unsigned int new_index) { if (old_index > new_index) { - set_clkdiv(new_index); - set_apll(new_index); + set_clkdiv(exynos_info, new_index); + set_apll(exynos_info, new_index); } else if (old_index < new_index) { - set_apll(new_index); - set_clkdiv(new_index); + set_apll(exynos_info, new_index); + set_clkdiv(exynos_info, new_index); } }