From patchwork Thu Apr 30 07:05:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 6300051 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 42B249F326 for ; Thu, 30 Apr 2015 07:06:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5200C201C8 for ; Thu, 30 Apr 2015 07:06:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 53AAE201C0 for ; Thu, 30 Apr 2015 07:06:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750771AbbD3HFk (ORCPT ); Thu, 30 Apr 2015 03:05:40 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:59053 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750705AbbD3HFi (ORCPT ); Thu, 30 Apr 2015 03:05:38 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NNL00KHIYDBK450@mailout4.w1.samsung.com>; Thu, 30 Apr 2015 08:05:35 +0100 (BST) X-AuditID: cbfec7f4-f79c56d0000012ee-ec-5541d4431d98 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id FB.2D.04846.344D1455; Thu, 30 Apr 2015 08:05:39 +0100 (BST) Received: from localhost.localdomain ([10.252.80.64]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NNL003CTYD3LC20@eusync2.samsung.com>; Thu, 30 Apr 2015 08:05:35 +0100 (BST) From: Krzysztof Kozlowski To: Kukjin Kim , Russell King , Javier Martinez Canillas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Chanwoo Choi , Inki Dae , Marek Szyprowski , Bartlomiej Zolnierkiewicz , Andrzej Hajda , Krzysztof Kozlowski Subject: [PATCH v3 1/2] ARM: EXYNOS: Get current parent clock for power domain on/off Date: Thu, 30 Apr 2015 16:05:24 +0900 Message-id: <1430377525-3145-1-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprJLMWRmVeSWpSXmKPExsVy+t/xK7rOVxxDDZ6vkLC4te4cq8XGGetZ La5/ec5qMf8IkDvp/gQWi6O/CyxevzC06H/8mtli0+NrrBaXd81hs5hxfh+Txe3LvBZrj9xl d+D1aGnuYfP4+/w6i8emVZ1sHpuX1Hv0bVnF6PF5k1wAWxSXTUpqTmZZapG+XQJXxubpqgVr 5CvOT+RrYJwi2cXIySEhYCLx/sFXNghbTOLCvfVANheHkMBSRomLx18wQTj/GSVeru5jAali EzCW2Lx8CViHiEAvk8SOG3kgRcwCHUwSjz7OYwVJCAuES6w69I0dxGYRUJX4t3sb0CQODl4B N4m9H2wgtslJnDw2mXUCI/cCRoZVjKKppckFxUnpuYZ6xYm5xaV56XrJ+bmbGCEB9mUH4+Jj VocYBTgYlXh4GaY5hgqxJpYVV+YeYpTgYFYS4ZVYDxTiTUmsrEotyo8vKs1JLT7EKM3BoiTO O3fX+xAhgfTEktTs1NSC1CKYLBMHp1QDow/H+so1lr78fGx9aqnpJVN0o/Kny50L/JKpn3Th Onfn6pmLNj1Z/TXMZMOVKQ4nou4GZCw8f/7j0fIZvPcuKX87LtObf+lX8dL/4icjuS+E/fT6 06H8ZsnhRdcVXM7ozndn66jWeuz+7VUYo8CvZWv6fWucuJKlt2VvL1r5sKa6ZWd1xDWL00os xRmJhlrMRcWJABHYb0QsAgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Using a fixed (by DTS) parent for clocks when turning on the power domain may introduce issues in other drivers. For example when such driver changes the parent during runtime and expects that he is the only place of such change. Do not rely on DTS providing the fixed parent for such clocks. Instead before switching domain off, grab a current parent of a clock with clk_get_parent(). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas --- Changes since v2: 1. Don't store the parent of the clock on driver init but instead mark it as -EINVAL. This means that on first power up of the domain (when system is booted with domain being off) the parent won't be set. This is a special rare condition because all domains are being turned on: either by reset value or by bootloader. Javier's reviewed by retained. 2. Add Javier's tags. Changes since v1: 1. Drop "pclk" bindings entirely as suggested by Andrzej Hajda. This was significant change so I did not add Javier's reviewed/tested tags. --- .../devicetree/bindings/arm/exynos/power_domain.txt | 7 ++++--- arch/arm/mach-exynos/pm_domains.c | 16 +++++++++------- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt index 5da38c5ed476..e151057d92f0 100644 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt @@ -19,9 +19,10 @@ Optional Properties: domains. - clock-names: The following clocks can be specified: - oscclk: Oscillator clock. - - pclkN, clkN: Pairs of parent of input clock and input clock to the - devices in this power domain. Maximum of 4 pairs (N = 0 to 3) - are supported currently. + - clkN: Input clocks to the devices in this power domain. These clocks + will be reparented to oscclk before swithing power domain off. + Their original parent will be brought back after turning on + the domain. Maximum of 4 clocks (N = 0 to 3) are supported. - asbN: Clocks required by asynchronous bridges (ASB) present in the power domain. These clock should be enabled during power domain on/off operations. diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index cbe56b35aea0..294fc7e956aa 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -62,6 +62,7 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { if (IS_ERR(pd->clk[i])) break; + pd->pclk[i] = clk_get_parent(pd->clk[i]); if (clk_set_parent(pd->clk[i], pd->oscclk)) pr_err("%s: error setting oscclk as parent to clock %d\n", pd->name, i); @@ -90,6 +91,9 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { if (IS_ERR(pd->clk[i])) break; + + if (IS_ERR(pd->clk[i])) + continue; /* Skip on first power up */ if (clk_set_parent(pd->clk[i], pd->pclk[i])) pr_err("%s: error setting parent to clock%d\n", pd->name, i); @@ -161,13 +165,11 @@ static __init int exynos4_pm_init_power_domain(void) pd->clk[i] = clk_get(dev, clk_name); if (IS_ERR(pd->clk[i])) break; - snprintf(clk_name, sizeof(clk_name), "pclk%d", i); - pd->pclk[i] = clk_get(dev, clk_name); - if (IS_ERR(pd->pclk[i])) { - clk_put(pd->clk[i]); - pd->clk[i] = ERR_PTR(-EINVAL); - break; - } + /* + * Skip setting parent on first power up. + * The parent at this time may not be useful at all. + */ + pd->pclk[i] = ERR_PTR(-EINVAL); } if (IS_ERR(pd->clk[0]))