From patchwork Wed Aug 26 17:43:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Padovan X-Patchwork-Id: 7078821 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F390CBEEC1 for ; Wed, 26 Aug 2015 17:43:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DF58020943 for ; Wed, 26 Aug 2015 17:43:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 886662094D for ; Wed, 26 Aug 2015 17:43:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752627AbbHZRnp (ORCPT ); Wed, 26 Aug 2015 13:43:45 -0400 Received: from mail-qg0-f67.google.com ([209.85.192.67]:34327 "EHLO mail-qg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752307AbbHZRnp (ORCPT ); Wed, 26 Aug 2015 13:43:45 -0400 Received: by qgi69 with SMTP id 69so10838348qgi.1 for ; Wed, 26 Aug 2015 10:43:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gU8mABbKzz715pHkVeMqyUxiTvxqGZoz0Cwx21i+Jv0=; b=CrJUehj/2mawVvk66Exoxj5xMXL9L5EnY4w16AsSgR+EeIB9l8LZsS7uRYs4IJ1FpW cVWV0tPUXfhLVz646e9oefn3l5tpKzCrkOzITW8mELEDrOwQPPC2y6c88gon/+6moNNy 9Xb7il5lXjVfRZ+dWwhgDqUPxIxw/VfsSxT1l/RG78cs/At9E2VJzzON94bD51O9cVTT HAvHskynGkkjI4bSs/hhsY8wlOLheIF81UBZB4qxXCrB39eka/UDwhqiSDrRXQkLmIve ux1HvPKIoCNjnY7XyYPmPVGe+cu1HAcOUDTCbWlH2j3xBdE7tuRnDzybsa0RcSKnKkkL SqYA== X-Received: by 10.140.234.139 with SMTP id f133mr84109603qhc.61.1440611024586; Wed, 26 Aug 2015 10:43:44 -0700 (PDT) Received: from jade.localdomain ([179.98.13.55]) by smtp.gmail.com with ESMTPSA id o96sm16856202qgd.23.2015.08.26.10.43.42 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Aug 2015 10:43:43 -0700 (PDT) From: Gustavo Padovan To: linux-samsung-soc@vger.kernel.org Cc: dri-devel@lists.freedesktop.org, inki.dae@samsung.com, jy0922.shim@samsung.com, tjakobi@math.uni-bielefeld.de, Gustavo Padovan Subject: [PATCH v2 03/11] drm/exynos: add begin and flush phases for planes Date: Wed, 26 Aug 2015 14:43:20 -0300 Message-Id: <1440611008-3473-5-git-send-email-gustavo@padovan.org> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1440611008-3473-1-git-send-email-gustavo@padovan.org> References: <1440611008-3473-1-git-send-email-gustavo@padovan.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gustavo Padovan .atomic_begin() and .atomic_flush() allows to perform extra operations before and after the update of planes. For FIMD for example this will be used to enable disable the shadow protection bit. Signed-off-by: Gustavo Padovan --- v2: rename prepare_plane/cleanup_plane to atomic_begin/atomic_flush --- drivers/gpu/drm/exynos/exynos_drm_crtc.c | 19 +++++++++++++++++++ drivers/gpu/drm/exynos/exynos_drm_drv.h | 6 ++++++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index 94eb831..54485b7 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -73,16 +73,35 @@ static void exynos_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); + struct drm_plane *plane; if (crtc->state->event) { WARN_ON(drm_crtc_vblank_get(crtc) != 0); exynos_crtc->event = crtc->state->event; } + + drm_atomic_crtc_for_each_plane(plane, crtc) { + struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane); + + if (exynos_crtc->ops->atomic_begin) + exynos_crtc->ops->atomic_begin(exynos_crtc, + exynos_plane); + } } static void exynos_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { + struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); + struct drm_plane *plane; + + drm_atomic_crtc_for_each_plane(plane, crtc) { + struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane); + + if (exynos_crtc->ops->atomic_flush) + exynos_crtc->ops->atomic_flush(exynos_crtc, + exynos_plane); + } } static struct drm_crtc_helper_funcs exynos_crtc_helper_funcs = { diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index a993aac..28afecc 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -87,6 +87,8 @@ struct exynos_drm_plane { * @disable_vblank: specific driver callback for disabling vblank interrupt. * @wait_for_vblank: wait for vblank interrupt to make sure that * hardware overlay is updated. + * @atomic_begin: prepare a window to receive a update + * @atomic_flush: mark the end of a window update * @update_plane: apply hardware specific overlay data to registers. * @disable_plane: disable hardware specific overlay. * @te_handler: trigger to transfer video image at the tearing effect @@ -107,10 +109,14 @@ struct exynos_drm_crtc_ops { int (*enable_vblank)(struct exynos_drm_crtc *crtc); void (*disable_vblank)(struct exynos_drm_crtc *crtc); void (*wait_for_vblank)(struct exynos_drm_crtc *crtc); + void (*atomic_begin)(struct exynos_drm_crtc *crtc, + struct exynos_drm_plane *plane); void (*update_plane)(struct exynos_drm_crtc *crtc, struct exynos_drm_plane *plane); void (*disable_plane)(struct exynos_drm_crtc *crtc, struct exynos_drm_plane *plane); + void (*atomic_flush)(struct exynos_drm_crtc *crtc, + struct exynos_drm_plane *plane); void (*te_handler)(struct exynos_drm_crtc *crtc); void (*clock_enable)(struct exynos_drm_crtc *crtc, bool enable); };