From patchwork Thu Oct 15 10:31:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 7404571 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B81E5BEEA4 for ; Thu, 15 Oct 2015 10:32:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4DDED20851 for ; Thu, 15 Oct 2015 10:32:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 396D220843 for ; Thu, 15 Oct 2015 10:32:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750960AbbJOKcM (ORCPT ); Thu, 15 Oct 2015 06:32:12 -0400 Received: from mail-wi0-f170.google.com ([209.85.212.170]:32869 "EHLO mail-wi0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752257AbbJOKcK (ORCPT ); Thu, 15 Oct 2015 06:32:10 -0400 Received: by wijp11 with SMTP id p11so22480310wij.0; Thu, 15 Oct 2015 03:32:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=xmEXxBG32tHQdHsDSvXemKRJSgeEVNTIcYluwjWoDbM=; b=bup76LhheF8k3nVhZ4Wr4VCZ926q+8szpG4fYNhvCUJq24m4XOsNQdoTdBcFVW1jsJ 47q8b9XMPHvsANb7XUaaAb7Y+Gb+phQX7bYq8gzstboKDLekeJigzb92R7zMAe5x0XB0 2HKwBuJ4R80yUEEFD/463K5+WLjxV8eynuvVOPBUSpGaN5tl09yRdh8f85JK9Yx6spgj jL7oU36t3krtgQLJTX6BgU057DjhQ79KPJIF/2IX/24/RkH4rJksKJlV8gHtjhmFXMJz CoS/yjTH544Qt8vGs6ZVNGNuSToFlPrYSfNS1uV5JYdrZtZpDw7dLRx1xkXtuDSIlAay XTNg== X-Received: by 10.180.107.1 with SMTP id gy1mr35279857wib.56.1444905128325; Thu, 15 Oct 2015 03:32:08 -0700 (PDT) Received: from cizrna.lan ([109.72.12.112]) by smtp.gmail.com with ESMTPSA id q1sm15604481wje.39.2015.10.15.03.32.06 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Oct 2015 03:32:07 -0700 (PDT) From: Tomeu Vizoso To: linux-kernel@vger.kernel.org Cc: Gustavo Padovan , Javier Martinez Canillas , Seung-Woo Kim , Kukjin Kim , Inki Dae , Kyungmin Park , Krzysztof Kozlowski , Joonyoung Shim , Tomeu Vizoso , devicetree@vger.kernel.org, Michael Turquette , Stephen Boyd , Kumar Gala , Ian Campbell , linux-samsung-soc@vger.kernel.org, Sylwester Nawrocki , Pawel Moll , Rob Herring , Mark Rutland , Tomasz Figa , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks Date: Thu, 15 Oct 2015 12:31:23 +0200 Message-Id: <1444905084-22540-2-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1444905084-22540-1-git-send-email-tomeu.vizoso@collabora.com> References: <1444905084-22540-1-git-send-email-tomeu.vizoso@collabora.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When the DISP1 power domain is powered off, there's two clocks that need to be temporarily reparented to OSC, and back to their original parents when the domain is powered on again. We expose these two clocks in the DT bindings so that the DT node of the power domain can reference them. Signed-off-by: Tomeu Vizoso Acked-by: Stephen Boyd Reviewed-by: Krzysztof Kozlowski --- Changes in v2: - Reuse mout_aclk200_p - Rename div_aclk300 as div_aclk300_disp drivers/clk/samsung/clk-exynos5250.c | 14 +++++++++++++- include/dt-bindings/clock/exynos5250.h | 4 +++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 55b83c7ef878..5bebf8cb0d70 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -222,9 +222,13 @@ PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" }; PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" }; PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" }; PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" }; +PNAME(mout_aclk300_p) = { "mout_aclk300_disp1_mid", + "mout_aclk300_disp1_mid1" }; PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" }; PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" }; PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" }; +PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" }; +PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" }; PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" }; PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" }; PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; @@ -303,9 +307,13 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { */ MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), + MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1), + MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1), MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1), + MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1, + 8, 1), MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1), MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1), @@ -316,7 +324,10 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1), - MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1), + MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub", + mout_aclk200_sub_p, SRC_TOP3, 4, 1), + MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub", + mout_aclk300_sub_p, SRC_TOP3, 6, 1), MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1), MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1), MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p, @@ -392,6 +403,7 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = { DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3), DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0, 24, 3), + DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3), DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3), DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3), diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h index 8183d1c237d9..15508adcdfde 100644 --- a/include/dt-bindings/clock/exynos5250.h +++ b/include/dt-bindings/clock/exynos5250.h @@ -173,8 +173,10 @@ /* mux clocks */ #define CLK_MOUT_HDMI 1024 #define CLK_MOUT_GPLL 1025 +#define CLK_MOUT_ACLK200_DISP1_SUB 1026 +#define CLK_MOUT_ACLK300_DISP1_SUB 1027 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 1026 +#define CLK_NR_CLKS 1028 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */