From patchwork Thu Dec 10 16:58:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartlomiej Zolnierkiewicz X-Patchwork-Id: 7820201 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7A75EBEEE1 for ; Thu, 10 Dec 2015 17:02:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6708E205B8 for ; Thu, 10 Dec 2015 17:02:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8E729205DD for ; Thu, 10 Dec 2015 17:02:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752867AbbLJRCP (ORCPT ); Thu, 10 Dec 2015 12:02:15 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:51351 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753736AbbLJRAd (ORCPT ); Thu, 10 Dec 2015 12:00:33 -0500 Received: from epcpsbgm2new.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZ502GN6J8AYQA0@mailout3.samsung.com>; Fri, 11 Dec 2015 02:00:31 +0900 (KST) X-AuditID: cbfee61b-f793c6d00000236c-e1-5669afafcfbf Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 16.52.09068.FAFA9665; Fri, 11 Dec 2015 02:00:31 +0900 (KST) Received: from AMDC1976.DIGITAL.local ([106.120.53.102]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZ500CRQJ7YAR80@mmp2.samsung.com>; Fri, 11 Dec 2015 02:00:31 +0900 (KST) From: Bartlomiej Zolnierkiewicz To: Thomas Abraham , Sylwester Nawrocki , Mike Turquette , Kukjin Kim , Kukjin Kim , Viresh Kumar , Krzysztof Kozlowski , Ben Gamari Cc: Tomasz Figa , Lukasz Majewski , Heiko Stuebner , Chanwoo Choi , Kevin Hilman , Javier Martinez Canillas , Tobias Jakobi , Anand Moon , linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, b.zolnierkie@samsung.com, Doug Anderson , Andreas Faerber Subject: [PATCH v5 3/7] ARM: dts: Exynos542x/5800: add CPU OPP properties Date: Thu, 10 Dec 2015 17:58:45 +0100 Message-id: <1449766729-435-4-git-send-email-b.zolnierkie@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1449766729-435-1-git-send-email-b.zolnierkie@samsung.com> References: <1449766729-435-1-git-send-email-b.zolnierkie@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpmkeLIzCtJLcpLzFFi42I5/e+xoO769ZlhBvva9S2aNxVbbJyxntVi 1vy7LBbXvzxntTi77CCbxf9Hr1kt3rxdw2Tx+oWhRe+Cq2wW/Y9fM1t8PbyC0eLNw82MFpse X2O1uLxrDpvF594jjBYzzu9jsli38Ra7xcVTrhaH37SzWnQsY7RoW/2B1WLVrj+MFhu/ejiI e7y/0cruMbvhIovHzll32T02repk87hzbQ+bx+Yl9R7/jrF7bOkHCvdtWcXocea3s8f2a/OY PTafrvb4vEkugDeKyyYlNSezLLVI3y6BK+Pf3XdsBT3WFZ3bchoY/+p2MXJySAiYSLz628cE YYtJXLi3ng3EFhKYxSix56RgFyMXkP2LUeLbg6UsIAk2ASuJie2rGEFsEYETTBJTNvmBFDEL 7GCRaJz6CqxbWMBT4sylV6wgNouAqsTbzg7mLkYODl4BN4n1q4wglslJnDw2GayEU8BdYuvf r+wgJUJAJcufxk9g5F3AyLCKUSK1ILmgOCk91ygvtVyvODG3uDQvXS85P3cTIzhqnknvYDy8 y/0QowAHoxIPb6JVZpgQa2JZcWXuIUYJDmYlEd4tM4BCvCmJlVWpRfnxRaU5qcWHGKU5WJTE efddigwTEkhPLEnNTk0tSC2CyTJxcEo1MHY4l77cxnjvjV6U2aSa1uVM95ewt7xYaZtpWxqT lu1erBs4r4yj7o6L4KYpnnEfTnvPW3bR647HtX2pjx54H9t7ePGPv7VfuDvUpr4NT45z2iqq mOrxJOqkIYuTw+ssRu8VRjVn2LRkOr6dM7u46WsJ7/2Vsoqa8tG38njULiifyZTK25Z9Soml OCPRUIu5qDgRAJmx+qmWAgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thomas Abraham For Exynos542x/5800 platforms, add CPU operating points for migrating from Exynos specific cpufreq driver to using generic cpufreq driver. Changes by Bartlomiej: - split Exynos5420 support from the original patch - merged Exynos5422 fixes from Ben Changes by Ben Gamari: - Port to operating-points-v2 Cc: Kukjin Kim Cc: Doug Anderson Cc: Javier Martinez Canillas Cc: Andreas Faerber Signed-off-by: Thomas Abraham Signed-off-by: Ben Gamari Signed-off-by: Bartlomiej Zolnierkiewicz Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 122 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 +++ 2 files changed, 132 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 48a0a55..616c2d0 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -50,6 +50,116 @@ usbdrdphy1 = &usbdrd_phy1; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + opp@1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <140000>; + }; + opp@1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <1212500>; + clock-latency-ns = <140000>; + }; + opp@1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1175000>; + clock-latency-ns = <140000>; + }; + opp@1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1137500>; + clock-latency-ns = <140000>; + }; + opp@1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1112500>; + clock-latency-ns = <140000>; + }; + opp@1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <140000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1037500>; + clock-latency-ns = <140000>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1012500>; + clock-latency-ns = <140000>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = < 987500>; + clock-latency-ns = <140000>; + }; + opp@900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = < 962500>; + clock-latency-ns = <140000>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = < 937500>; + clock-latency-ns = <140000>; + }; + opp@700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = < 912500>; + clock-latency-ns = <140000>; + }; + }; + + cpu1_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + opp@1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1275000>; + clock-latency-ns = <140000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1212500>; + clock-latency-ns = <140000>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1162500>; + clock-latency-ns = <140000>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1112500>; + clock-latency-ns = <140000>; + }; + opp@900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <140000>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1025000>; + clock-latency-ns = <140000>; + }; + opp@700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <975000>; + clock-latency-ns = <140000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <937500>; + clock-latency-ns = <140000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -58,8 +168,11 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu-cluster.0"; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu1: cpu@1 { @@ -68,6 +181,7 @@ reg = <0x1>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu2: cpu@2 { @@ -76,6 +190,7 @@ reg = <0x2>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu3: cpu@3 { @@ -84,14 +199,18 @@ reg = <0x3>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x100>; + clocks = <&clock CLK_KFC_CLK>; + clock-names = "cpu-cluster.1"; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cpu1_opp_table>; }; cpu5: cpu@101 { @@ -100,6 +219,7 @@ reg = <0x101>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cpu1_opp_table>; }; cpu6: cpu@102 { @@ -108,6 +228,7 @@ reg = <0x102>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cpu1_opp_table>; }; cpu7: cpu@103 { @@ -116,6 +237,7 @@ reg = <0x103>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cpu1_opp_table>; }; }; diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index b7f60c8..9a5131d 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -20,8 +20,10 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x100>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cpu1_opp_table>; }; &cpu1 { @@ -30,6 +32,7 @@ reg = <0x101>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cpu1_opp_table>; }; &cpu2 { @@ -38,6 +41,7 @@ reg = <0x102>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cpu1_opp_table>; }; &cpu3 { @@ -46,14 +50,17 @@ reg = <0x103>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cpu1_opp_table>; }; &cpu4 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cpu0_opp_table>; }; &cpu5 { @@ -62,6 +69,7 @@ reg = <0x1>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cpu0_opp_table>; }; &cpu6 { @@ -70,6 +78,7 @@ reg = <0x2>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cpu0_opp_table>; }; &cpu7 { @@ -78,4 +87,5 @@ reg = <0x3>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cpu0_opp_table>; };