From patchwork Fri Dec 11 05:07:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 7825761 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 50068BEEE1 for ; Fri, 11 Dec 2015 05:25:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 13E73203C2 for ; Fri, 11 Dec 2015 05:25:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A1313204E7 for ; Fri, 11 Dec 2015 05:25:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753807AbbLKFZA (ORCPT ); Fri, 11 Dec 2015 00:25:00 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:59510 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753140AbbLKFJI (ORCPT ); Fri, 11 Dec 2015 00:09:08 -0500 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZ6008ALGZ6LW80@mailout2.samsung.com>; Fri, 11 Dec 2015 14:09:06 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.113]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id FE.AC.04964.27A5A665; Fri, 11 Dec 2015 14:09:06 +0900 (KST) X-AuditID: cbfee68f-f793a6d000001364-08-566a5a72c719 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 40.CB.09068.17A5A665; Fri, 11 Dec 2015 14:09:06 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZ6007QUGY7NJ40@mmp2.samsung.com>; Fri, 11 Dec 2015 14:09:05 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 09/20] PM / devfreq: exynos: Update documentation for bus devices using passive governor Date: Fri, 11 Dec 2015 14:07:48 +0900 Message-id: <1449810479-14763-10-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1449810479-14763-1-git-send-email-cw00.choi@samsung.com> References: <1449810479-14763-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHIsWRmVeSWpSXmKPExsWyRsSkULcoKivM4M5WQYvrX56zWsw/co7V ov/NQlaLc69WMlq8fmFo0f/4NbPF2aY37BaXd81hs/jce4TRYsb5fUwW6zbeYre4fZnXYun1 i0wWtxtXsFlMmL6WxaJ17xF2i7bVH1gdBD3WzFvD6NHS3MPmcbmvl8lj56y77B4rl39h89i0 qpPN498xdo++LasYPT5vkgvgjOKySUnNySxLLdK3S+DKWNDdwV7w3r3iyab5TA2Mx8y7GDk5 JARMJE6daWSCsMUkLtxbz9bFyMUhJLCCUeLNwsdMMEVXrvxmhEjMYpTo3b0AquoLo8TT610s IFVsAloS+1/cYAOxRQTcJb7e2w1WxCzwhUmidfJ35i5GDg5hgVyJHSvA6lkEVCUentzHDmLz CrhJXGlbDbVNTuLDnkfsIOWcQPGuM/kgYSEBV4np++6zgoyUEGjkkDj55QE7xBwBiW+TD7GA 1EsIyEpsOsAMMUZS4uCKGywTGIUXMDKsYhRNLUguKE5KLzLWK07MLS7NS9dLzs/dxAiMttP/ nvXvYLx7wPoQowAHoxIPrwdbVpgQa2JZcWXuIUZToA0TmaVEk/OBMZ1XEm9obGZkYWpiamxk bmmmJM67UOpnsJBAemJJanZqakFqUXxRaU5q8SFGJg5OqQZGASHJv+HT33/YOnHKnJ1+lV1K R9O9QxZWKMx9ULFfdZbvgXeWVSztIfzGm1sED+1d82ypPvusG8F7X+jatNUZZ8hnzq15KHnn Xwufh4dyrtj6qe93f9pl2u6sHvd918c10a8OT1wWX2B9Mswm8MjjV9Ibdu27z3jhr/jWr1+F 28KMRerOd93/qMRSnJFoqMVcVJwIACZYCXexAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNIsWRmVeSWpSXmKPExsVy+t9jQd2iqKwwg5NLOCyuf3nOajH/yDlW i/43C1ktzr1ayWjx+oWhRf/j18wWZ5vesFtc3jWHzeJz7xFGixnn9zFZrNt4i93i9mVei6XX LzJZ3G5cwWYxYfpaFovWvUfYLdpWf2B1EPRYM28No0dLcw+bx+W+XiaPnbPusnusXP6FzWPT qk42j3/H2D36tqxi9Pi8SS6AM6qB0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJc SSEvMTfVVsnFJ0DXLTMH6BUlhbLEnFKgUEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGEN Y8aC7g72gvfuFU82zWdqYDxm3sXIySEhYCJx5cpvRghbTOLCvfVsXYxcHEICsxglencvgHK+ MEo8vd7FAlLFJqAlsf/FDTYQW0TAXeLrvd1gRcwCX5gkWid/Z+5i5OAQFsiV2LECrJ5FQFXi 4cl97CA2r4CbxJW21UwQ2+QkPux5xA5SzgkU7zqTDxIWEnCVmL7vPusERt4FjAyrGCVSC5IL ipPSc43yUsv1ihNzi0vz0vWS83M3MYIj+pn0DsbDu9wPMQpwMCrx8C7gyAoTYk0sK67MPcQo wcGsJMK7OxAoxJuSWFmVWpQfX1Sak1p8iNEU6K6JzFKiyfnAZJNXEm9obGJmZGlkbmhhZGyu JM6771JkmJBAemJJanZqakFqEUwfEwenVAOjZvHZK3K7JSf7/2NXP5vgn818+JyY0qrdritk A+5Pdq06I92Ywi39v+978oJb3fvPOz4ySOa79Q+oI6J0WlLWiv33i6NXeIaqPp+648EFTr7z hYL/lren/WVq8j32aJ/Ftuqjmp15ax7LGxiHHJSVmmp0YzcPj+WLNNU07hmR7Ze26AXfeqvE UpyRaKjFXFScCAD4s4hD/gIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch updates the documentation for passive bus devices and adds the detailed example of Exynos3250. Signed-off-by: Chanwoo Choi --- .../devicetree/bindings/devfreq/exynos-bus.txt | 250 ++++++++++++++++++++- 1 file changed, 247 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt index e32daef328da..a251f9120561 100644 --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -8,22 +8,46 @@ of each buses on runtime. When gathering the usage of each buses on runtime, the driver uses the PPMU (Platform Performance Monitoring Unit) which is able to measure the current load of sub-blocks. +The Exynos SoC includes the various sub-blocks which have the each AXI bus. +The each AXI bus has the owned source clock but, has not the only owned +power line. The power line might be shared among one more sub-blocks. +So, we can divide into two type of device as the role of each sub-block. +There are two type of bus devices as following: +- parent bus device +- passive bus device + +Basically, parent and passive bus device share the same power line. +The parent bus device can only change the voltage of shared power line +and the rest bus devices (passive bus device) depend on the decision of +the parent bus device. If there are three blocks which share the VDD_xxx +power line, Only one block should be parent device and then the rest blocks +should depend on the parent device as passive device. + + VDD_xxx |--- A block (parent) + |--- B block (passive) + |--- C block (passive) + There are a little different composition among Exynos SoC because each Exynos SoC has the different sub-blocks. So, this difference should be specified in devicetree file instead of each device driver. In result, this driver is able to support the bus frequency for all Exynos SoCs. -Required properties for bus device: +Required properties for all bus devices: - compatible: Should be "samsung,exynos-bus". - clock-names : the name of clock used by the bus, "bus". - clocks : phandles for clock specified in "clock-names" property. - operating-points-v2: the OPP table including frequency/voltage information to support DVFS (Dynamic Voltage/Frequency Scaling) feature. + +Required properties only for parent bus device: - vdd-supply: the regulator to provide the buses with the voltage. - devfreq-events: the devfreq-event device to monitor the current utilization of buses. -Optional properties for bus device: +Required properties only for passive bus device: +- devfreq: the parent bus device. + +Optional properties only for parent bus device: - exynos,saturation-ratio: the percentage value which is used to calibrate the performance count against total cycle count. @@ -32,7 +56,20 @@ Example1: power line (regulator). The MIF (Memory Interface) AXI bus is used to transfer data between DRAM and CPU and uses the VDD_MIF regualtor. - - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block + - MIF (Memory Interface) block + : VDD_MIF |--- DMC (Dynamic Memory Controller) + + - INT (Internal) block + : VDD_INT |--- LEFTBUS (parent device) + |--- PERIL + |--- MFC + |--- G3D + |--- RIGHTBUS + |--- FSYS + |--- LCD0 + |--- PERIR + |--- ISP + |--- CAM - MIF bus's frequency/voltage table ----------------------- @@ -45,6 +82,24 @@ Example1: |L5| 400000 |875000 | ----------------------- + - INT bus's frequency/voltage table + ---------------------------------------------------------- + |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP |PERIL ||VDD_INT | + | name| |LCD0 | | | || | + | | |FSYS | | | || | + | | |MFC | | | || | + ---------------------------------------------------------- + |Mode |*parent|passive |passive|passive|passive|| | + ---------------------------------------------------------- + |Lv |Frequency ||Voltage | + ---------------------------------------------------------- + |L1 |50000 |50000 |50000 |50000 |50000 ||900000 | + |L2 |80000 |80000 |80000 |80000 |80000 ||900000 | + |L3 |100000 |100000 |100000 |100000 |100000 ||1000000 | + |L4 |134000 |134000 |200000 |200000 | ||1000000 | + |L5 |200000 |200000 |400000 |300000 | ||1000000 | + ---------------------------------------------------------- + Example2 : The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi is listed below: @@ -83,6 +138,154 @@ Example2 : }; }; + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_160>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mcuisp: bus_mcuisp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; + clock-names = "bus"; + operating-points-v2 = <&bus_mcuisp_opp_table>; + status = "disabled"; + }; + + bus_isp: bus_isp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_isp_opp_table>; + status = "disabled"; + }; + + bus_peril: bus_peril { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peril_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_mcuisp_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; + + bus_isp_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_peril_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + + Usage case to handle the frequency and voltage of bus on runtime in exynos3250-rinato.dts is listed below: @@ -91,3 +294,44 @@ Example2 : vdd-supply = <&buck1_reg>; /* VDD_MIF */ status = "okay"; }; + + &bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; + }; + + &bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; + }; + + &bus_lcd0 { + devfreq = <&bus_leftbus>; + status = "okay"; + }; + + &bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; + }; + + &bus_mcuisp { + devfreq = <&bus_leftbus>; + status = "okay"; + }; + + &bus_isp { + devfreq = <&bus_leftbus>; + status = "okay"; + }; + + &bus_peril { + devfreq = <&bus_leftbus>; + status = "okay"; + }; + + &bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; + };