From patchwork Fri Dec 11 05:07:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 7825951 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0AC5C9F349 for ; Fri, 11 Dec 2015 05:28:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2DC0820395 for ; Fri, 11 Dec 2015 05:28:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 35627204E3 for ; Fri, 11 Dec 2015 05:28:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753176AbbLKFIu (ORCPT ); Fri, 11 Dec 2015 00:08:50 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:34219 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753095AbbLKFIq (ORCPT ); Fri, 11 Dec 2015 00:08:46 -0500 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZ6004Y3GYLSY80@mailout3.samsung.com>; Fri, 11 Dec 2015 14:08:45 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.115]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 43.1A.04790.C5A5A665; Fri, 11 Dec 2015 14:08:45 +0900 (KST) X-AuditID: cbfee691-f79766d0000012b6-cd-566a5a5cc70f Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 3A.9B.09068.C5A5A665; Fri, 11 Dec 2015 14:08:44 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZ6007QUGY7NJ40@mmp2.samsung.com>; Fri, 11 Dec 2015 14:08:44 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 03/20] ARM: dts: Add DMC bus node for Exynos3250 Date: Fri, 11 Dec 2015 14:07:42 +0900 Message-id: <1449810479-14763-4-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1449810479-14763-1-git-send-email-cw00.choi@samsung.com> References: <1449810479-14763-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHIsWRmVeSWpSXmKPExsWyRsSkWDc2KivMoG8ik8X1L89ZLeYfOcdq 0f9mIavFuVcrGS1evzC06H/8mtnibNMbdovLu+awWXzuPcJoMeP8PiaLdRtvsVvcvsxrsfT6 RSaL240r2CwmTF/LYtG69wi7RdvqD6wOgh5r5q1h9Ghp7mHzuNzXy+Sxc9Zddo+Vy7+weWxa 1cnm8e8Yu0ffllWMHp83yQVwRnHZpKTmZJalFunbJXBlnDxvWdDBW7Fw4QOWBsZpXF2MnBwS AiYSLWtmskHYYhIX7q0Hsrk4hARWMEq8OjGPDabo2rPfjBCJWUCJg80sEM4XRont5+Yzg1Sx CWhJ7H9xA6xDRMBd4uu93WCjmAW+MEm0Tv4OViQs4Cxx/eMtRhCbRUBV4srl42ANvAKuEouf TWSEWCcn8WHPI/YuRg4OTgE3ia4z+SBhIaCS6fvus4LMlBD4yy6xfN0qJog5AhLfJh9iAamX EJCV2HSAGWKMpMTBFTdYJjAKL2BkWMUomlqQXFCclF5kqlecmFtcmpeul5yfu4kRGG2n/z2b uIPx/gHrQ4wCHIxKPLwLOLLChFgTy4orcw8xmgJtmMgsJZqcD4zpvJJ4Q2MzIwtTE1NjI3NL MyVxXh3pn8FCAumJJanZqakFqUXxRaU5qcWHGJk4OKUaGPN2ehg7GO3dL60fVl/7u9ZGVqIp eX7By8Pe/9+HeCmqF35NKnXlV32+8+TXl143VaZMu3P69UHHFTOO5S36nX3gXsln5uZlp3vU kq3jbm+ZX/TORntawk39LFGLOWma+yXrL/ZMfBJ2en7XpZr4Bnn7Z5tzHK+VXpdbUnTmKLur yhGbLR8uXFZiKc5INNRiLipOBADdqpchsQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNIsWRmVeSWpSXmKPExsVy+t9jQd2YqKwwg5d7LS2uf3nOajH/yDlW i/43C1ktzr1ayWjx+oWhRf/j18wWZ5vesFtc3jWHzeJz7xFGixnn9zFZrNt4i93i9mVei6XX LzJZ3G5cwWYxYfpaFovWvUfYLdpWf2B1EPRYM28No0dLcw+bx+W+XiaPnbPusnusXP6FzWPT qk42j3/H2D36tqxi9Pi8SS6AM6qB0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJc SSEvMTfVVsnFJ0DXLTMH6BUlhbLEnFKgUEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGEN Y8bJ85YFHbwVCxc+YGlgnMbVxcjJISFgInHt2W9GCFtM4sK99WxdjFwcQgKzGCVeHWxmgXC+ MEpsPzefGaSKTUBLYv+LG2wgtoiAu8TXe7vBOpgFvjBJtE7+DlYkLOAscf3jLbCxLAKqElcu Hwdr4BVwlVj8bCLUOjmJD3sesXcxcnBwCrhJdJ3JBwkLAZVM33efdQIj7wJGhlWMEqkFyQXF Sem5Rnmp5XrFibnFpXnpesn5uZsYwRH9THoH4+Fd7ocYBTgYlXh4F3BkhQmxJpYVV+YeYpTg YFYS4d0dCBTiTUmsrEotyo8vKs1JLT7EaAp010RmKdHkfGCyySuJNzQ2MTOyNDI3tDAyNlcS 5913KTJMSCA9sSQ1OzW1ILUIpo+Jg1OqgZH30noF44IrwgleEh9V/vfk7LTkO7uSx+/gu6z9 b63U+hWj5tzZ9zZZ+e4KC5m6kunufrNLc5L1L5nJ/fhaNjf5ufbXDnvH21dVeQRydIukt6nF RYQr+S0JF+H+9j5h4lmhtsodjYertnokzFRmfCohInzR8v5ktreGv1YFhConnqxS5PZfpMRS nJFoqMVcVJwIAEDPHpf+AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC. The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard SDRAM devices. The bus includes the OPP tables and the source clock for DMC block. Following list specifies the detailed relation between the clock and DMC block: - The source clock of DMC block : div_dmc Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 18e3deffbf48..262b3b1995fd 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -701,6 +701,40 @@ clock-names = "ppmu"; status = "disabled"; }; + + bus_dmc: bus_dmc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_dmc CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_dmc_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <800000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <800000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <800000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <825000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <875000>; + }; + }; }; };