From patchwork Mon Dec 14 06:38:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 7841511 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C20AABEEE1 for ; Mon, 14 Dec 2015 06:41:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DE2B320374 for ; Mon, 14 Dec 2015 06:41:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DF3AC20546 for ; Mon, 14 Dec 2015 06:41:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752797AbbLNGjX (ORCPT ); Mon, 14 Dec 2015 01:39:23 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:55793 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932119AbbLNGjT (ORCPT ); Mon, 14 Dec 2015 01:39:19 -0500 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZC00DTE55H6690@mailout3.samsung.com>; Mon, 14 Dec 2015 15:39:17 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.113]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 39.CF.04964.5146E665; Mon, 14 Dec 2015 15:39:17 +0900 (KST) X-AuditID: cbfee68f-f793a6d000001364-b6-566e6415a211 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 7A.2E.09068.5146E665; Mon, 14 Dec 2015 15:39:17 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZC00FY8541SY80@mmp2.samsung.com>; Mon, 14 Dec 2015 15:39:17 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 13/20] ARM: dts: Add bus nodes using VDD_INT for Exynos3250 Date: Mon, 14 Dec 2015 15:38:17 +0900 Message-id: <1450075104-13705-14-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1450075104-13705-1-git-send-email-cw00.choi@samsung.com> References: <1450075104-13705-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHIsWRmVeSWpSXmKPExsWyRsSkUFc0JS/M4MFWBYvrX56zWsw/co7V ov/NQlaLc69WMlq8fmFo0f/4NbPF2aY37BaXd81hs/jce4TRYsb5fUwW6zbeYre4fZnXYun1 i0wWtxtXsFlMmL6WxaJ17xF2i7bVH1gdBD3WzFvD6NHS3MPmcbmvl8lj56y77B4rl39h89i0 qpPN498xdo++LasYPT5vkgvgjOKySUnNySxLLdK3S+DKuLFkMnvBWuWK5sl/mRoYv0l1MXJy SAiYSNzqm80MYYtJXLi3nq2LkYtDSGAFo8S9PWdZuxg5wIq+bqqCiM9ilDgzcxIzhPOFUeLW krfsIN1sAloS+1/cYAOxRQTcJb7e2w02iVngC5NE6+TvYCuEBfwkFu86wApiswioSrSuOM0I soFXwE1i+UxRiCvkJD7seQQ2kxMovO/rdLCZQgKuEofnfwdbLCHQyiHx89NxRog5AhLfJh9i gbhUVmLTAahvJCUOrrjBMoFReAEjwypG0dSC5ILipPQiY73ixNzi0rx0veT83E2MwGg7/e9Z /w7GuwesDzEKcDAq8fBmLMsNE2JNLCuuzD3EaAq0YSKzlGhyPjCm80riDY3NjCxMTUyNjcwt zZTEeRdK/QwWEkhPLEnNTk0tSC2KLyrNSS0+xMjEwSnVwFhos0768qMZjLrSWyf112S0FbT5 bHgvzy/2OrPO6vtPN6fTfusW+lm+3Z7ip9x/Vta8aAbfqZLUH/HM8stkJp5iK9R3sf8VW7fu 8s0JEyY1r7m2ZUasR3rdqefXef/u425+X7FnxyoBkQ2eC7Oqq4ukLPK2yKlL/FY93/Nhv6Ny VdztGfrpd5VYijMSDbWYi4oTAZqEnmSxAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNIsWRmVeSWpSXmKPExsVy+t9jQV3RlLwwg54dUhbXvzxntZh/5Byr Rf+bhawW516tZLR4/cLQov/xa2aLs01v2C0u75rDZvG59wijxYzz+5gs1m28xW5x+zKvxdLr F5ksbjeuYLOYMH0ti0Xr3iPsFm2rP7A6CHqsmbeG0aOluYfN43JfL5PHzll32T1WLv/C5rFp VSebx79j7B59W1YxenzeJBfAGdXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGu pJCXmJtqq+TiE6DrlpkD9IqSQlliTilQKCCxuFhJ3w7ThNAQN10LmMYIXd+QILgeIwM0kLCG MePGksnsBWuVK5on/2VqYPwm1cXIwSEhYCLxdVNVFyMnkCkmceHeerYuRi4OIYFZjBJnZk5i hnC+MErcWvKWHaSKTUBLYv+LG2wgtoiAu8TXe7vBOpgFvjBJtE7+zgySEBbwk1i86wAriM0i oCrRuuI0I8g2XgE3ieUzRSG2yUl82PMIbCYnUHjf1+lgM4UEXCUOz//OPIGRdwEjwypGidSC 5ILipPRco7zUcr3ixNzi0rx0veT83E2M4Ih+Jr2D8fAu90OMAhyMSjy8mctyw4RYE8uKK3MP MUpwMCuJ8CZY5YUJ8aYkVlalFuXHF5XmpBYfYjQFumsis5Rocj4w2eSVxBsam5gZWRqZG1oY GZsrifPuuxQZJiSQnliSmp2aWpBaBNPHxMEp1cCouv71hd2m8dPn/j9zdeu72X+SDod69rkF zbCPLos1NlLYV+z1kPHgOc6Xa2S5mGLapH6crJK6/NTm1N0g191yf88uKeposcuxT4q1sZn7 fBNfZTqj1LyGDa4WjXpzrxzVXx5vWLEsYsXH886TNStUWj7vDFCaeJWpeNUy53p7jg8MXo7H 3m1SYinOSDTUYi4qTgQAXIOYCf4CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bus nodes using VDD_INT for Exynos3250 SoC. Exynos3250 has following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK400 clock for MCUISP - ACLK266 clock for ISP - ACLK200 clock for FSYS - ACLK160 clock for LCD0 - ACLK100 clock for PERIL - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 147 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 262b3b1995fd..5cc98cf13173 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -735,6 +735,153 @@ opp-microvolt = <875000>; }; }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_160>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mcuisp: bus_mcuisp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; + clock-names = "bus"; + operating-points-v2 = <&bus_mcuisp_opp_table>; + status = "disabled"; + }; + + bus_isp: bus_isp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_isp_opp_table>; + status = "disabled"; + }; + + bus_peril: bus_peril { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peril_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_mcuisp_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; + + bus_isp_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_peril_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; }; };