From patchwork Mon Dec 14 06:38:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 7841491 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 26CE0BEEE1 for ; Mon, 14 Dec 2015 06:41:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 512B02054D for ; Mon, 14 Dec 2015 06:41:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3DF6020374 for ; Mon, 14 Dec 2015 06:41:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752759AbbLNGli (ORCPT ); Mon, 14 Dec 2015 01:41:38 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:49695 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932125AbbLNGjb (ORCPT ); Mon, 14 Dec 2015 01:39:31 -0500 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZC00PEG55P5E80@mailout1.samsung.com>; Mon, 14 Dec 2015 15:39:25 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.113]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 07.DF.04964.D146E665; Mon, 14 Dec 2015 15:39:25 +0900 (KST) X-AuditID: cbfee68f-f793a6d000001364-12-566e641d0dca Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 00.3E.09068.C146E665; Mon, 14 Dec 2015 15:39:24 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZC00FY8541SY80@mmp2.samsung.com>; Mon, 14 Dec 2015 15:39:24 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 15/20] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12 Date: Mon, 14 Dec 2015 15:38:19 +0900 Message-id: <1450075104-13705-16-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1450075104-13705-1-git-send-email-cw00.choi@samsung.com> References: <1450075104-13705-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLIsWRmVeSWpSXmKPExsWyRsSkUFc2JS/M4Op1NovrX56zWsw/co7V ov/NQlaLc69WMlq8fmFo0f/4NbPF2aY37BaXd81hs/jce4TRYsb5fUwW6zbeYre4fZnXYun1 i0wWtxtXsFlMmL6WxaJ17xF2i7bVH1gdBD3WzFvD6NHS3MPmcbmvl8lj56y77B4rl39h89i0 qpPN498xdo++LasYPT5vkgvgjOKySUnNySxLLdK3S+DK+P1hNmvBfJmKZz2yDYx7xboYOTkk BEwk7nWeYoOwxSQu3FsPZHNxCAmsYJR4sb+NGabowOq/7BCJWYwS1743giWEBL4wSux5qARi swloSex/cQNskoiAu8TXe7vBJjELfGGSaJ38HaxBWMBP4tOfhUA2BweLgKrElhcxIGFeATeJ r7NnsEAsk5P4sOcRO4jNCRTf93U6G8QuV4nD80HGcAHV/GWXuLyrlREkwSIgIPFt8iEWkJkS ArISmw5AHS0pcXDFDZYJjMILGBlWMYqmFiQXFCelFxnrFSfmFpfmpesl5+duYgTG2ul/z/p3 MN49YH2IUYCDUYmHN2NZbpgQa2JZcWXuIUZToA0TmaVEk/OBEZ1XEm9obGZkYWpiamxkbmmm JM67UOpnsJBAemJJanZqakFqUXxRaU5q8SFGJg5OqQZGHxOTq7IOby79PDndrmfdabY79e0z fi/5+sB6yp5FEQVuEVc2bdjOxdiTFZvTvdb9S8GVCb95uCqXcjIuc/34T5M/gp8h0nOCR2+6 +vXf8T4ZDwVWtPHLXEnTF/7CmrxodYxi8M8Vn3jUd204nJN3Q+uYaLPUB/uJb5beZjV+sY9P zm6JzvofSizFGYmGWsxFxYkAaYmnq7ACAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJIsWRmVeSWpSXmKPExsVy+t9jQV3ZlLwwg8ViFte/PGe1mH/kHKtF /5uFrBbnXq1ktHj9wtCi//FrZouzTW/YLS7vmsNm8bn3CKPFjPP7mCzWbbzFbnH7Mq/F0usX mSxuN65gs5gwfS2LReveI+wWbas/sDoIeqyZt4bRo6W5h83jcl8vk8fOWXfZPVYu/8LmsWlV J5vHv2PsHn1bVjF6fN4kF8AZ1cBok5GamJJapJCal5yfkpmXbqvkHRzvHG9qZmCoa2hpYa6k kJeYm2qr5OIToOuWmQP0iZJCWWJOKVAoILG4WEnfDtOE0BA3XQuYxghd35AguB4jAzSQsIYx 4/eH2awF82UqnvXINjDuFeti5OSQEDCROLD6LzuELSZx4d56ti5GLg4hgVmMEte+NzKDJIQE vjBK7HmoBGKzCWhJ7H9xgw3EFhFwl/h6bzdYA7PAFyaJ1snfwRqEBfwkPv1ZCGRzcLAIqEps eREDEuYVcJP4OnsGC8QyOYkPex6BLeYEiu/7Op0NYperxOH535knMPIuYGRYxSiRWpBcUJyU nmuUl1quV5yYW1yal66XnJ+7iREczc+kdzAe3uV+iFGAg1GJhzdzWW6YEGtiWXFl7iFGCQ5m JRHeBKu8MCHelMTKqtSi/Pii0pzU4kOMpkB3TWSWEk3OByaavJJ4Q2MTMyNLI3NDCyNjcyVx 3n2XIsOEBNITS1KzU1MLUotg+pg4OKUaGON6OWz7Aj77fDEy/DOp95zTwo2SOVOLQyPruAVM FgoUqW/W15I+2X1T9ILI+vzIpT/fprQnvnxixFlXsq0hyL00LKXnstrWbzXGKYYGqv4+k7/G ef7v8vP2ljTSNeBsSd4p9CJNyHjuqfLu0x2X1WpNrr5llZd8xHq2R7fCoT208VLJw7VKLMUZ iYZazEXFiQBGTMqw/AIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bus nodes using VDD_INT for Exynos4x12 SoC. Exynos4x12 has the following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD : The minimum clock of ACLK160 should be over 160MHz. When drop the clock under 160MHz, show the broken image. - ACLK133 clock for FSYS - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi [linux.amoon: Tested on Odroid U3] Tested-by: Anand Moon Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4x12.dtsi | 106 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 99a0f4ca3d47..e5173107ed44 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -349,6 +349,112 @@ opp-hz = /bits/ 64 <267000000>; }; }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + }; + + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <925000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_display_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_fsys_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + + bus_peri_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; }; &combiner {