From patchwork Wed Dec 23 12:31:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yakir Yang X-Patchwork-Id: 7911371 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 83504BEEE5 for ; Wed, 23 Dec 2015 12:34:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7963E204A7 for ; Wed, 23 Dec 2015 12:33:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 64AE420453 for ; Wed, 23 Dec 2015 12:33:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755310AbbLWMcM (ORCPT ); Wed, 23 Dec 2015 07:32:12 -0500 Received: from lucky1.263xmail.com ([211.157.147.131]:45003 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932886AbbLWMb7 (ORCPT ); Wed, 23 Dec 2015 07:31:59 -0500 Received: from ykk?rock-chips.com (unknown [192.168.167.236]) by lucky1.263xmail.com (Postfix) with SMTP id 64D7B87DD8; Wed, 23 Dec 2015 20:31:53 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id DF959438; Wed, 23 Dec 2015 20:31:51 +0800 (CST) X-RL-SENDER: ykk@rock-chips.com X-FST-TO: inki.dae@samsung.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: ykk@rock-chips.com X-UNIQUE-TAG: <13d593d79686f254de4b835895984214> X-ATTACHMENT-NUM: 0 X-SENDER: ykk@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 15234V4J3ZS; Wed, 23 Dec 2015 20:31:54 +0800 (CST) From: Yakir Yang To: Inki Dae , Mark Yao , Jingoo Han , Heiko Stuebner Cc: Thierry Reding , Krzysztof Kozlowski , Rob Herring , Russell King , emil.l.velikov@gmail.com, Gustavo Padovan , Kishon Vijay Abraham I , javier@osg.samsung.com, Andy Yan , Yakir Yang , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v12 03/18] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Date: Wed, 23 Dec 2015 20:31:50 +0800 Message-Id: <1450873910-18979-1-git-send-email-ykk@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1450873538-18304-1-git-send-email-ykk@rock-chips.com> References: <1450873538-18304-1-git-send-email-ykk@rock-chips.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP link_rate and lane_count already configured in analogix_dp_set_link_train(), so we don't need to config those repeatly after training finished, just remove them out. Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}. Signed-off-by: Yakir Yang Tested-by: Javier Martinez Canillas --- Changes in v12: - Remove the enum link_rate_type struct, using the marcos in drm_dp_helper.h (Jingoo) Changes in v11: None Changes in v10: None Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: - Update commit message more readable. (Jingoo) - Adjust the order from 05 to 04 Changes in v3: - The link_rate and lane_count shouldn't config to the DT property value directly, but we can take those as hardware limite. For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would like "link-rate = 0x0a" "lane-count = 4". (Thierry) Changes in v2: None drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 14 +++++++------- drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 7 +------ drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 2 +- 3 files changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index 915fb46..fac8ad4 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -627,6 +627,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, /* * For DP rev.1.1, Maximum link rate of Main Link lanes * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + * For DP rev.1.2, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps */ analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); *bandwidth = data; @@ -647,7 +649,7 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, static void analogix_dp_init_training(struct analogix_dp_device *dp, enum link_lane_count_type max_lane, - enum link_rate_type max_rate) + int max_rate) { /* * MACRO_RST must be applied after the PLL_LOCK to avoid @@ -659,11 +661,12 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp, analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); - if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && - (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { + if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && + (dp->link_train.link_rate != DP_LINK_BW_2_7) && + (dp->link_train.link_rate != DP_LINK_BW_5_4)) { dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", dp->link_train.link_rate); - dp->link_train.link_rate = LINK_RATE_1_62GBPS; + dp->link_train.link_rate = DP_LINK_BW_1_62; } if (dp->link_train.lane_count == 0) { @@ -901,9 +904,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) analogix_dp_enable_rx_to_enhanced_mode(dp, 1); analogix_dp_enable_enhanced_mode(dp, 1); - analogix_dp_set_lane_count(dp, dp->video_info->lane_count); - analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate); - analogix_dp_init_video(dp); ret = analogix_dp_config_video(dp); if (ret) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h index f7dfc8e..911642e 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h @@ -20,11 +20,6 @@ #define MAX_CR_LOOP 5 #define MAX_EQ_LOOP 5 -enum link_rate_type { - LINK_RATE_1_62GBPS = 0x06, - LINK_RATE_2_70GBPS = 0x0a -}; - enum link_lane_count_type { LANE_COUNT1 = 1, LANE_COUNT2 = 2, @@ -128,7 +123,7 @@ struct video_info { enum color_coefficient ycbcr_coeff; enum color_depth color_depth; - enum link_rate_type link_rate; + int link_rate; enum link_lane_count_type lane_count; }; diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c index a388c0a..eb0b63c 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c @@ -855,7 +855,7 @@ void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) u32 reg; reg = bwtype; - if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS)) + if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62)) writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET); }