From patchwork Thu Mar 31 02:47:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 8707091 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 22170C0553 for ; Thu, 31 Mar 2016 02:49:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4FD1220251 for ; Thu, 31 Mar 2016 02:49:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 647912020F for ; Thu, 31 Mar 2016 02:49:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755546AbcCaCsT (ORCPT ); Wed, 30 Mar 2016 22:48:19 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:52227 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755378AbcCaCsR (ORCPT ); Wed, 30 Mar 2016 22:48:17 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O4V005MNUGAEZ20@mailout1.samsung.com>; Thu, 31 Mar 2016 11:48:10 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.112]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id D0.AB.04785.9EF8CF65; Thu, 31 Mar 2016 11:48:09 +0900 (KST) X-AuditID: cbfee68e-f79d96d0000012b1-93-56fc8fe97d3b Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 6B.9A.06699.9EF8CF65; Thu, 31 Mar 2016 11:48:09 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O4V00BJVUG94S30@mmp2.samsung.com>; Thu, 31 Mar 2016 11:48:09 +0900 (KST) From: Chanwoo Choi To: k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: jh80.chung@samsung.com, andi.shyti@samsung.com, inki.dae@samsung.com, sw0312.kim@samsung.com, pankaj.dubey@samsung.com, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 2/9] dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250 Date: Thu, 31 Mar 2016 11:47:58 +0900 Message-id: <1459392485-11327-3-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1459392485-11327-1-git-send-email-cw00.choi@samsung.com> References: <1459392485-11327-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFLMWRmVeSWpSXmKPExsWyRsSkQPdl/58wgynPrS22H3nGanH9y3NW i/lHzrFaTLo/gcXixq82VovXLwwt+h+/ZrbY9Pgaq8XlXXPYLGac38dksWjrF3aLw2/aWS1m TH7JZrFq1x9GBz6PnbPusntsWtXJ5rF5Sb1H35ZVjB6fN8kFsEZx2aSk5mSWpRbp2yVwZbyZ vpK1oIOn4sqRu+wNjAc4uxg5OSQETCSutW1hhbDFJC7cW8/WxcjFISSwglFi59w25i5GDrCi PXtjQGqEBGYxSnzYHwJhf2GU6LzlCWKzCWhJ7H9xgw3EFhGIk5h4EcJmFpjFJDFvfiGILSwQ IbH1xzmwOIuAqkT36Q6wvbwCrhLr125jhLhBTuLDnkfsIDangJvEvRWX2SF2uUqsmTmHGeQ2 CYFT7BLLf81lhBgkIPFt8iEWiDtlJTYdYIaYIylxcMUNlgmMwgsYGVYxiqYWJBcUJ6UXGekV J+YWl+al6yXn525iBEbJ6X/P+nYw3jxgfYhRgINRiYdXI+1PmBBrYllxZe4hRlOgDROZpUST 84GxmFcSb2hsZmRhamJqbGRuaaYkzpsg9TNYSCA9sSQ1OzW1ILUovqg0J7X4ECMTB6dUA+Ns fW930Zccbg/4W34fbK0L1NyzTeuWDVfuS5tvu//v8l62pWJXhfGDgkwJaeGUy3MSjsz7VP2p +du91QYPqzsfPSxxtwpn5fn79pt0qrbjGas5boL+c4y6hNOqi7dsbyw5vP59z/HnWwz6n96P OqnKevvVbofv528uKhecIRgV/LLs4tOvLoVKLMUZiYZazEXFiQBqOKjAjQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOIsWRmVeSWpSXmKPExsVy+t9jQd2X/X/CDG7fNLPYfuQZq8X1L89Z LeYfOcdqMen+BBaLG7/aWC1evzC06H/8mtli0+NrrBaXd81hs5hxfh+TxaKtX9gtDr9pZ7WY Mfklm8WqXX8YHfg8ds66y+6xaVUnm8fmJfUefVtWMXp83iQXwBrVwGiTkZqYklqkkJqXnJ+S mZduq+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg65aZA3SokkJZYk4pUCggsbhYSd8O04TQ EDddC5jGCF3fkCC4HiMDNJCwhjHjzfSVrAUdPBVXjtxlb2A8wNnFyMEhIWAisWdvTBcjJ5Ap JnHh3no2EFtIYBajxIf9IRD2F0aJzlueIDabgJbE/hc3wGpEBOIkJl6EsJkFZjFJzJtfCGIL C0RIbP1xDizOIqAq0X26gxXE5hVwlVi/dhsjxC45iQ97HrGD2JwCbhL3Vlxmh9jlKrFm5hzm CYy8CxgZVjFKpBYkFxQnpeca5aWW6xUn5haX5qXrJefnbmIER+Iz6R2Mh3e5H2IU4GBU4uG9 kPwnTIg1say4MvcQowQHs5IIb2gfUIg3JbGyKrUoP76oNCe1+BCjKdBhE5mlRJPzgUkiryTe 0NjEzMjSyNzQwsjYXEmc9/H/dWFCAumJJanZqakFqUUwfUwcnFINjP27TAT3223w2SNVbHe1 xyqi5NSOe6ztzk9ePiw4k9MoveZgZ93Wo99Tv964tvma5WJfPZbIv5XBMyruf7h5Ncn+1J8/ +oufPt9RfHs+w67DE7u8zdU39ai49a2vVvzwpLhQO2zFmvmrOGeV11x53qN77OP5kgUTD522 9jqp5eczny/C6J7O1GdKLMUZiYZazEXFiQDGzb4D2gIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the new clock id for both UART2 and MM2 device for Exynos3250 SoC. Signed-off-by: Chanwoo Choi --- include/dt-bindings/clock/exynos3250.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index 63d01c15d2b3..c796ff02ceeb 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -79,6 +79,8 @@ #define CLK_MOUT_CORE 58 #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 +#define CLK_MOUT_UART2 61 +#define CLK_MOUT_MMC2 62 /* Dividers */ #define CLK_DIV_GPL 64 @@ -127,6 +129,9 @@ #define CLK_DIV_CORE 107 #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 +#define CLK_DIV_UART2 110 +#define CLK_DIV_MMC2_PRE 111 +#define CLK_DIV_MMC2 112 /* Gates */ #define CLK_ASYNC_G3D 128 @@ -223,6 +228,8 @@ #define CLK_BLOCK_MFC 219 #define CLK_BLOCK_CAM 220 #define CLK_SMIES 221 +#define CLK_UART2 222 +#define CLK_SDMMC2 223 /* Special clocks */ #define CLK_SCLK_JPEG 224 @@ -249,12 +256,14 @@ #define CLK_SCLK_SPI0 245 #define CLK_SCLK_UART1 246 #define CLK_SCLK_UART0 247 +#define CLK_SCLK_UART2 248 +#define CLK_SCLK_MMC2 249 /* * Total number of clocks of main CMU. * NOTE: Must be equal to last clock ID increased by one. */ -#define CLK_NR_CLKS 248 +#define CLK_NR_CLKS 250 /* * CMU DMC