From patchwork Thu Mar 31 02:48:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 8706981 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5EE3E9F36E for ; Thu, 31 Mar 2016 02:48:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 851BC202BE for ; Thu, 31 Mar 2016 02:48:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A604F2020F for ; Thu, 31 Mar 2016 02:48:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754114AbcCaCsO (ORCPT ); Wed, 30 Mar 2016 22:48:14 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:54319 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752003AbcCaCsM (ORCPT ); Wed, 30 Mar 2016 22:48:12 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O4V02LY1UGA8140@mailout3.samsung.com>; Thu, 31 Mar 2016 11:48:10 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.112]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 53.AB.04785.AEF8CF65; Thu, 31 Mar 2016 11:48:10 +0900 (KST) X-AuditID: cbfee68e-f79d96d0000012b1-9d-56fc8fea1a1e Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 5D.9A.06699.AEF8CF65; Thu, 31 Mar 2016 11:48:10 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O4V00BJVUG94S30@mmp2.samsung.com>; Thu, 31 Mar 2016 11:48:09 +0900 (KST) From: Chanwoo Choi To: k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: jh80.chung@samsung.com, andi.shyti@samsung.com, inki.dae@samsung.com, sw0312.kim@samsung.com, pankaj.dubey@samsung.com, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 4/9] clk: samsung: exynos3250: Add MMC2 clock Date: Thu, 31 Mar 2016 11:48:00 +0900 Message-id: <1459392485-11327-5-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1459392485-11327-1-git-send-email-cw00.choi@samsung.com> References: <1459392485-11327-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJLMWRmVeSWpSXmKPExsWyRsSkQPdV/58wg09HZCy2H3nGanH9y3NW i/lHzrFaTLo/gcXixq82VovXLwwt+h+/ZrbY9Pgaq8XlXXPYLGac38dksWjrF3aLw2/aWS1m TH7JZrFq1x9GBz6PnbPusntsWtXJ5rF5Sb1H35ZVjB6fN8kFsEZx2aSk5mSWpRbp2yVwZRza /56pYL1wxcmd7cwNjKcEuhg5OCQETCTe3JHrYuQEMsUkLtxbz9bFyMUhJLCCUeL7q81sEAkT ibMzVzNDJGYxShz+tpgJJCEk8IVRovOWJ4jNJqAlsf/FDbAGEYE4iYkXIWxmgVlMEvPmF4LY wgIOEncvHmMCWcwioCqxer8MiMkr4CrxYKMexCo5iQ97HrGD2JwCbhL3Vlxmh9jkKrFm5hyw EyQEzrFL7Jk3lxUkwSIgIPFt8iEWiF9kJTYdYIaYIylxcMUNlgmMwgsYGVYxiqYWJBcUJ6UX GekVJ+YWl+al6yXn525iBMbI6X/P+nYw3jxgfYhRgINRiYdXI+1PmBBrYllxZe4hRlOgDROZ pUST84GRmFcSb2hsZmRhamJqbGRuaaYkzpsg9TNYSCA9sSQ1OzW1ILUovqg0J7X4ECMTB6dU A+MUZh5Vc54HQUfrJ6RoOZ+z2pJkKeCl7/9BcIJlOnd/KV/1xn2meYcC37xMPTxNUXZ+zlfG Bm7bKcmnmSdyRjtpSjmJM98UZXn0t8HtuXzHaualT85tS5duWz93967g1IsJH5ZVXTzi/eDG jPr4KL++n6zNs/t+30r8ue5D00+hpYav158wW6LEUpyRaKjFXFScCADUN4VBjAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOIsWRmVeSWpSXmKPExsVy+t9jQd1X/X/CDC7dFbPYfuQZq8X1L89Z LeYfOcdqMen+BBaLG7/aWC1evzC06H/8mtli0+NrrBaXd81hs5hxfh+TxaKtX9gtDr9pZ7WY Mfklm8WqXX8YHfg8ds66y+6xaVUnm8fmJfUefVtWMXp83iQXwBrVwGiTkZqYklqkkJqXnJ+S mZduq+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg65aZA3SokkJZYk4pUCggsbhYSd8O04TQ EDddC5jGCF3fkCC4HiMDNJCwhjHj0P73TAXrhStO7mxnbmA8JdDFyMkhIWAicXbmamYIW0zi wr31bF2MXBxCArMYJQ5/W8wEkhAS+MIo0XnLE8RmE9CS2P/iBhuILSIQJzHxIoTNLDCLSWLe /EIQW1jAQeLuxWNAvRwcLAKqEqv3y4CYvAKuEg826kGskpP4sOcRO4jNKeAmcW/FZXaITa4S a2bOYZ7AyLuAkWEVo0RqQXJBcVJ6rlFearlecWJucWleul5yfu4mRnAkPpPewXh4l/shRgEO RiUe3gvJf8KEWBPLiitzDzFKcDArifCG9gGFeFMSK6tSi/Lji0pzUosPMZoCnTWRWUo0OR+Y JPJK4g2NTcyMLI3MDS2MjM2VxHkf/18XJiSQnliSmp2aWpBaBNPHxMEp1cBYmzZfik+h2cuK byJ79ArbJ5yLn8y+GaJ7/eqeU4kTvtU/3bXwn8RBwfDO+bXczMsPrryddGbbxace5ne+nt6u /O3nk+8bU4UM31bfDAtYUZgYM9fOisspeWrFF369NNWgff+KPU7fedG2O1Zrro1NwpbiT5GM W46k7xP5zpTo7r/MxpIvIXatEktxRqKhFnNRcSIAKRQusdoCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos3250.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index bc60e399d1bc..16575ee874cb 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -302,6 +302,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { /* SRC_FSYS */ MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4), + MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4), MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4), MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), @@ -390,6 +391,11 @@ static struct samsung_div_clock div_clks[] __initdata = { CLK_SET_RATE_PARENT, 0), DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), + /* DIV_FSYS2 */ + DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8, + CLK_SET_RATE_PARENT, 0), + DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), + /* DIV_PERIL0 */ DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), @@ -540,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi", GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre", + GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre", GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre", @@ -635,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0), GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0), GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0), + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0), GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0), GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0), GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),