From patchwork Fri Apr 8 05:00:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 8780661 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 20A3A9FBEA for ; Fri, 8 Apr 2016 05:02:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 13D1C20274 for ; Fri, 8 Apr 2016 05:02:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D2EC82017E for ; Fri, 8 Apr 2016 05:02:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757211AbcDHFBi (ORCPT ); Fri, 8 Apr 2016 01:01:38 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:54672 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757160AbcDHFBC (ORCPT ); Fri, 8 Apr 2016 01:01:02 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O5A00ZHATXDWW40@mailout4.samsung.com>; Fri, 08 Apr 2016 14:00:49 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.115]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id AD.A5.04785.10B37075; Fri, 8 Apr 2016 14:00:49 +0900 (KST) X-AuditID: cbfee68e-f79d96d0000012b1-66-57073b0131e7 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id 7A.89.06682.10B37075; Fri, 8 Apr 2016 14:00:49 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O5A008B4TXCCJ50@mmp1.samsung.com>; Fri, 08 Apr 2016 14:00:48 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: rjw@rjwysocki.net, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, linux.amoon@gmail.com, m.reichl@fivetechno.de, tjakobi@math.uni-bielefeld.de, inki.dae@samsung.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 5/7] clk: samsung: exynos542x: Add the clock id for ACLK Date: Fri, 08 Apr 2016 14:00:44 +0900 Message-id: <1460091646-28701-6-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1460091646-28701-1-git-send-email-cw00.choi@samsung.com> References: <1460091646-28701-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNIsWRmVeSWpSXmKPExsWyRsSkWJfRmj3c4NJNfYvrX56zWsw/co7V ov/NQlaLc69WMlpMuj+BxeL1C0OL/sevmS3ONr1ht9j0+BqrxeVdc9gsPvceYbSYcX4fk8W6 jbfYLW5f5rV4eeQHo8XS6xeZLG43rmCzmDB9LYvFmdOXWC1a9x5htzj8pp3Vom31B1aLVbv+ MDqIe6yZt4bRo6W5h83jcl8vk8etO/UeO2fdZfdYufwLm8emVZ1sHpuX1Hv8O8buseVqO4tH 35ZVjB6fN8kF8ERx2aSk5mSWpRbp2yVwZeza8o254J9+xfJdx1kbGLdrdjFyckgImEg0LTnG CmGLSVy4t56ti5GLQ0hgBaPEpj3X2WGKrjx8zwiRWMoosWLzdCjnC6PEn5tnWECq2AS0JPa/ uAHWLiIwlVHi86k2FhCHWeAIs8TUjTeYQKqEBTwk1p57ygZiswioSjz+vg5sOa+Aq0T/kSVQ ++QkPux5BGZzCrhJfJ+wEKxXCKjmecMbqGOPcEicmyQDMUdA4tvkQ0DLOIDishKbDjBDlEhK HFxxg2UCo/ACRoZVjKKpBckFxUnpRUZ6xYm5xaV56XrJ+bmbGIFxfPrfs74djDcPWB9iFOBg VOLhvfCeLVyINbGsuDL3EKMp0IaJzFKiyfnAZJFXEm9obGZkYWpiamxkbmmmJM6bIPUzWEgg PbEkNTs1tSC1KL6oNCe1+BAjEwenVAOj9qmb9bWy14SlmSeFKGzZWsfpWWA961jshGdvt077 WFpc33qQrej6ueenZHWjvuZxn2R9JP5Mgi+7f3NWxx0XpeWt5hNWSX7q5Z9TpdgXe34Xx56t PL6XUk3tlkzedP+e06/4HKFJrqraXIKPbduqV08IabKcs4ChhGm96qZqo7TiVP6fDeuUWIoz Eg21mIuKEwEnNcSY3gIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprJKsWRmVeSWpSXmKPExsVy+t9jAV1Ga/Zwg70rNCyuf3nOajH/yDlW i/43C1ktzr1ayWgx6f4EFovXLwwt+h+/ZrY42/SG3WLT42usFpd3zWGz+Nx7hNFixvl9TBbr Nt5it7h9mdfi5ZEfjBZLr19ksrjduILNYsL0tSwWZ05fYrVo3XuE3eLwm3ZWi7bVH1gtVu36 w+gg7rFm3hpGj5bmHjaPy329TB637tR77Jx1l91j5fIvbB6bVnWyeWxeUu/x7xi7x5ar7Swe fVtWMXp83iQXwBPVwGiTkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk 4hOg65aZA/S1kkJZYk4pUCggsbhYSd8O04TQEDddC5jGCF3fkCC4HiMDNJCwhjFj15ZvzAX/ 9CuW7zrO2sC4XbOLkZNDQsBE4srD94wQtpjEhXvr2boYuTiEBJYySqzYPJ0RwvnCKPHn5hkW kCo2AS2J/S9ugFWJCExllPh8qo0FxGEWOMIsMXXjDSaQKmEBD4m1556ygdgsAqoSj7+vYwWx eQVcJfqPLGGH2Ccn8WHPIzCbU8BN4vuEhWC9QkA1zxvesE5g5F3AyLCKUSK1ILmgOCk91zAv tVyvODG3uDQvXS85P3cTIzhZPJPawXhwl/shRgEORiUe3gvv2cKFWBPLiitzDzFKcDArifA+ tGAPF+JNSaysSi3Kjy8qzUktPsRoCnTYRGYp0eR8YCLLK4k3NDYxM7I0Mje0MDI2VxLnffx/ XZiQQHpiSWp2ampBahFMHxMHp1QDo3gpp3Go2gTRbafnhnm0uEj5x+8zjV7nbpZ2ZEW9Aauw e/KLVf9SOxwaqpS3nnbgSl5nvG/NfivrNSkp9hu9+z/JPGk/fP0iu9Ey6eXz/L80Vs41rah9 ZbHUYaZw03eP7PQjJx0XhZ//P+NCR9bV/355lX8+TpK1f2RU4Wz9OX3y/PnTd1b5KLEUZyQa ajEXFScCABPL60ksAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the clock id for ACLK clock which is source clock of AMBA AXI Bus. This clock should be handled in Bus frequency scaling driver. Signed-off-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos5420.c | 85 +++++++++++++++++++++++------------- 1 file changed, 55 insertions(+), 30 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index be03ed0fcb6b..d7c62dfb1646 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -554,8 +554,9 @@ static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = { }; static struct samsung_div_clock exynos5800_div_clks[] __initdata = { - DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3), - + DIV_F(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", + "mout_aclk400_wcore", + DIV_TOP0, 16, 3, CLK_SET_RATE_PARENT, 0), DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", DIV_TOP8, 16, 3), DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", @@ -607,8 +608,9 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { }; static struct samsung_div_clock exynos5420_div_clks[] __initdata = { - DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll", - DIV_TOP0, 16, 3), + DIV_F(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", + "mout_aclk400_wcore_bpll", + DIV_TOP0, 16, 3, CLK_SET_RATE_PARENT, 0), }; static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { @@ -785,31 +787,52 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = { DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), - DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3), - DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), - DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), - DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), - DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3), - DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), - DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), - - DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", - DIV_TOP1, 0, 3), - DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp", - DIV_TOP1, 4, 3), - DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), - DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0", - DIV_TOP1, 16, 3), - DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), - DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), - DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), - - DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), - DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), - DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), - DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), - DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3), - DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), + DIV_F(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", + DIV_TOP0, 0, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", + DIV_TOP0, 4, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", + DIV_TOP0, 8, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", + "mout_aclk200_fsys2", + DIV_TOP0, 12, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", + DIV_TOP0, 20, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", + DIV_TOP0, 24, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", + DIV_TOP0, 28, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", + "mout_aclk333_432_gscl", + DIV_TOP1, 0, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", + "mout_aclk333_432_isp", + DIV_TOP1, 4, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", + DIV_TOP1, 8, 6, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", + "mout_aclk333_432_isp0", + DIV_TOP1, 16, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", + DIV_TOP1, 20, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", + DIV_TOP1, 24, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", + DIV_TOP1, 28, 3, CLK_SET_RATE_PARENT, 0), + + DIV_F(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", + DIV_TOP2, 8, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", + DIV_TOP2, 12, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, + 16, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", + DIV_TOP2, 20, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", + "mout_aclk300_disp1", + DIV_TOP2, 24, 3, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", + DIV_TOP2, 28, 3, CLK_SET_RATE_PARENT, 0), /* DISP1 Block */ DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), @@ -817,7 +840,9 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = { DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), - DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3), + DIV_F(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", + "mout_aclk400_disp1", + DIV_TOP2, 4, 3, CLK_SET_RATE_PARENT, 0), /* Audio Block */ DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),