From patchwork Mon Apr 11 03:57:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 8796511 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A3192C0553 for ; Mon, 11 Apr 2016 04:01:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A104120268 for ; Mon, 11 Apr 2016 04:01:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 99E2720254 for ; Mon, 11 Apr 2016 04:01:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752122AbcDKEBU (ORCPT ); Mon, 11 Apr 2016 00:01:20 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:41183 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751187AbcDKD6M (ORCPT ); Sun, 10 Apr 2016 23:58:12 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O5G01BZKB0QZZB0@mailout1.samsung.com>; Mon, 11 Apr 2016 12:58:02 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.115]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id DB.23.04789.9C02B075; Mon, 11 Apr 2016 12:58:01 +0900 (KST) X-AuditID: cbfee691-f795a6d0000012b5-35-570b20c911f3 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 69.29.06699.9C02B075; Mon, 11 Apr 2016 12:58:01 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O5G00DWZB0M9H20@mmp2.samsung.com>; Mon, 11 Apr 2016 12:58:01 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: rjw@rjwysocki.net, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, linux.amoon@gmail.com, m.reichl@fivetechno.de, tjakobi@math.uni-bielefeld.de, inki.dae@samsung.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v9 13/20] ARM: dts: Add bus nodes using VDD_INT for Exynos3250 Date: Mon, 11 Apr 2016 12:57:51 +0900 Message-id: <1460347078-15175-14-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1460347078-15175-1-git-send-email-cw00.choi@samsung.com> References: <1460347078-15175-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRmVeSWpSXmKPExsWyRsSkWPekAne4waULNhbXvzxntZh/5Byr Rf+bhawW516tZLSYdH8Ci8XrF4YW/Y9fM1ucbXrDbrHp8TVWi8u75rBZfO49wmgx4/w+Jot1 G2+xW9y+zGvx8sgPRoul1y8yWdxuXMFmMWH6WhaLM6cvsVq07j3CbnH4TTurRdvqD6wWq3b9 YXQQ91gzbw2jR0tzD5vH5b5eJo9bd+o9ds66y+6xcvkXNo9NqzrZPDYvqff4d4zdY8vVdhaP vi2rGD0+b5IL4InisklJzcksSy3St0vgypjefo61YK1yxfRHv1gbGL9JdTFycEgImEjcnVvR xcgJZIpJXLi3ng3EFhJYwShx56sATMmqreJdjFxA4VmMEgdffmSEqPnCKNH5LQnEZhPQktj/ 4gYbSJGIwFRGic+n2lhAHGaBI8wSUzfeYAKpEhbwk3i0eDIryFQWAVWJC5/NQExeATeJQweE IW6Qk/iw5xE7iM0JFP60vh2sWkjAVeLZ5zqQiRICRzgk9rafB7uTRUBA4tvkQywQd8pKbDrA DDFGUuLgihssExiFFzAyrGIUTS1ILihOSi8y1StOzC0uzUvXS87P3cQIjN3T/55N3MF4/4D1 IUYBDkYlHl6Ha1zhQqyJZcWVuYcYTYE2TGSWEk3OByaIvJJ4Q2MzIwtTE1NjI3NLMyVxXh3p n8FCAumJJanZqakFqUXxRaU5qcWHGJk4OKUaGAM7M6p9Fyz7y3FDdK313msejv8fb1U7Jvns 9CbV9Q1TP/VYnO9Zm3lrI8vrZbIn9n67qn3LhVvM0LTCtvF3ymxu/YJ/uwMWpOozGwZdF6jd LCaZz/LzmoX2k6f7ZA6bzfi7Yfm6KVe/cx5dIvPEwfPYKo1vvdcZXHZXPLuXwLne42KJWTur +RolluKMREMt5qLiRACBZIPX2AIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprCKsWRmVeSWpSXmKPExsVy+t9jQd2TCtzhBisWmVpc//Kc1WL+kXOs Fv1vFrJanHu1ktFi0v0JLBavXxha9D9+zWxxtukNu8Wmx9dYLS7vmsNm8bn3CKPFjPP7mCzW bbzFbnH7Mq/FyyM/GC2WXr/IZHG7cQWbxYTpa1kszpy+xGrRuvcIu8XhN+2sFm2rP7BarNr1 h9FB3GPNvDWMHi3NPWwel/t6mTxu3an32DnrLrvHyuVf2Dw2repk89i8pN7j3zF2jy1X21k8 +rasYvT4vEkugCeqgdEmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX0NLCXEkhLzE31VbJ xSdA1y0zB+hrJYWyxJxSoFBAYnGxkr4dpgmhIW66FjCNEbq+IUFwPUYGaCBhDWPG9PZzrAVr lSumP/rF2sD4TaqLkYNDQsBEYtVW8S5GTiBTTOLCvfVsXYxcHEICsxglDr78yAiSEBL4wijR +S0JxGYT0JLY/+IGWJGIwFRGic+n2lhAHGaBI8wSUzfeYAKpEhbwk3i0eDIryAYWAVWJC5/N QExeATeJQweEIZbJSXzY84gdxOYECn9a3w5WLSTgKvHsc90ERt4FjAyrGCVSC5ILipPSc43y Usv1ihNzi0vz0vWS83M3MYJTxDPpHYyHd7kfYhTgYFTi4X1xmStciDWxrLgy9xCjBAezkgjv A1nucCHelMTKqtSi/Pii0pzU4kOMpkBXTWSWEk3OB6avvJJ4Q2MTMyNLI3NDCyNjcyVx3sf/ 14UJCaQnlqRmp6YWpBbB9DFxcEo1MGor2bwNbRJ78OoqgyLfCQsVH5VJP9+/2nq13nRPmZfg opN/nZ+K9B2743lCaVFU5x/mLTONe9bq/G1SzJbeknLKd4LOtuwMgW/i1z0FbNT3/r4y++Iy 4/9iqQtUFpVxr7lfd9cgM65ZodL8T9EGm98ZczIsu6OkP7//MWeDqtFvQRNd1p8sHUosxRmJ hlrMRcWJADQSc+InAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bus nodes using VDD_INT for Exynos3250 SoC. Exynos3250 has following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK400 clock for MCUISP - ACLK266 clock for ISP - ACLK200 clock for FSYS - ACLK160 clock for LCD0 - ACLK100 clock for PERIL - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 147 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 1ae72c4fa55e..b5157492a422 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -722,6 +722,153 @@ opp-microvolt = <875000>; }; }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_160>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mcuisp: bus_mcuisp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; + clock-names = "bus"; + operating-points-v2 = <&bus_mcuisp_opp_table>; + status = "disabled"; + }; + + bus_isp: bus_isp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_isp_opp_table>; + status = "disabled"; + }; + + bus_peril: bus_peril { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peril_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_mcuisp_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; + + bus_isp_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_peril_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; }; };