From patchwork Tue May 31 21:48:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Javier Martinez Canillas X-Patchwork-Id: 9145721 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 47EA960752 for ; Tue, 31 May 2016 21:48:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A24120700 for ; Tue, 31 May 2016 21:48:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2ECAA26464; Tue, 31 May 2016 21:48:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AD9AA20700 for ; Tue, 31 May 2016 21:48:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756597AbcEaVsY (ORCPT ); Tue, 31 May 2016 17:48:24 -0400 Received: from lists.s-osg.org ([54.187.51.154]:53867 "EHLO lists.s-osg.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756618AbcEaVsX (ORCPT ); Tue, 31 May 2016 17:48:23 -0400 Received: from minerva.sisa.samsung.com (host-202.58.217.201.copaco.com.py [201.217.58.202]) by lists.s-osg.org (Postfix) with ESMTPSA id 316D4E2749; Tue, 31 May 2016 14:48:51 -0700 (PDT) From: Javier Martinez Canillas To: linux-kernel@vger.kernel.org Cc: Javier Martinez Canillas , devicetree@vger.kernel.org, Kukjin Kim , Krzysztof Kozlowski , Kumar Gala , Ian Campbell , linux-samsung-soc@vger.kernel.org, Rob Herring , Pawel Moll , Mark Rutland , Russell King , linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: dts: exynos: Add TMU nodes regulator supply for Peach boards Date: Tue, 31 May 2016 17:48:00 -0400 Message-Id: <1464731280-24588-1-git-send-email-javier@osg.samsung.com> X-Mailer: git-send-email 2.5.5 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Exynos5800 Peach Pi and Exynos5420 Peach Pit Chromebooks have the LDO10 1.8V output connected to the VDD18_TS{01,23,4} Exynos SoC pins. Add this regulator as the input supply of the Thermal Management Unit channels and also remove the always-on property since all the devices using LDO10 as input supply are now defined. Signed-off-by: Javier Martinez Canillas --- arch/arm/boot/dts/exynos5420-peach-pit.dts | 21 ++++++++++++++++++++- arch/arm/boot/dts/exynos5800-peach-pi.dts | 21 ++++++++++++++++++++- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index c1247402cb17..a55760b5fa82 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -425,7 +425,6 @@ regulator-name = "vdd_ldo10"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; regulator-state-mem { regulator-off-in-suspend; }; @@ -924,6 +923,26 @@ assigned-clock-parents = <&clock CLK_FIN_PLL>; }; +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo10_reg>; +}; + &rtc { status = "okay"; clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index af1c9b9a63f9..34cc6cee0cdb 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -425,7 +425,6 @@ regulator-name = "vdd_ldo10"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; regulator-state-mem { regulator-off-in-suspend; }; @@ -900,6 +899,26 @@ assigned-clock-parents = <&clock CLK_FIN_PLL>; }; +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo10_reg>; +}; + &rtc { status = "okay"; clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>;