From patchwork Wed Aug 10 14:48:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 9273715 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 10450600CB for ; Wed, 10 Aug 2016 19:25:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EB78E28338 for ; Wed, 10 Aug 2016 19:25:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DEC4328413; Wed, 10 Aug 2016 19:25:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C4AD328338 for ; Wed, 10 Aug 2016 19:25:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965227AbcHJS7J (ORCPT ); Wed, 10 Aug 2016 14:59:09 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:41463 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965156AbcHJS7E (ORCPT ); Wed, 10 Aug 2016 14:59:04 -0400 Received: from epcpsbgm2new.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0OBP030P97TFJ310@mailout1.samsung.com>; Wed, 10 Aug 2016 23:48:52 +0900 (KST) X-AuditID: cbfee61b-f79466d000001e3c-23-57ab3ed4ed17 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id C4.44.07740.4DE3BA75; Wed, 10 Aug 2016 07:48:52 -0700 (MST) Received: from AMDC1344.digital.local ([106.116.147.32]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OBP00DYX7SY4Z30@mmp1.samsung.com>; Wed, 10 Aug 2016 23:48:52 +0900 (KST) From: Sylwester Nawrocki To: lee.jones@linaro.org Cc: broonie@kernel.org, alsa-devel@alsa-project.org, robh@kernel.org, devicetree@vger.kernel.org, b.zolnierkie@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Sylwester Nawrocki , Inha Song , Beomho Seo Subject: [PATCH v6 2/2] mfd: Add Samsung Exynos Low Power Audio Subsystem driver Date: Wed, 10 Aug 2016 16:48:20 +0200 Message-id: <1470840500-2428-2-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1470840500-2428-1-git-send-email-s.nawrocki@samsung.com> References: <1470840500-2428-1-git-send-email-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrNLMWRmVeSWpSXmKPExsVy+t9jAd0rdqvDDbony1tcuXiIyWLjjPWs Fqc/bWO3mPrwCZvF/CPnWC12/b3PaHH/61FGi8u75rBZzDi/j8ni/54d7BaH37SzOnB7bPjc xOaxaVUnm8eda3vYPPq2rGL0+LxJLoA1issmJTUnsyy1SN8ugStjY/txloJrrhWb+2ezNzD+ texi5OSQEDCRaPj5ghXCFpO4cG89WxcjF4eQwFJGif5/X5ghnF+MEj9/32YCqWITMJToPdrH CGKLCEhIbPzRxwJSxCywk0niw5ovQO0cHMICARKdbcYgNSwCqhKXpu8F6+UVcJVYeWEP1DY5 iZPHJoPZnAJuEk+2bGcHsYWAag5tucoygZF3ASPDKkaJ1ILkguKk9FyjvNRyveLE3OLSvHS9 5PzcTYzgIHwmvYPx8C73Q4wCHIxKPLw7OFeFC7EmlhVX5h5ilOBgVhLhdbNZHS7Em5JYWZVa lB9fVJqTWnyIUZqDRUmc9/H/dWFCAumJJanZqakFqUUwWSYOTqkGxsSZvfM8y5qTU6ZJV+im /vF575y5adqW5Gs/0/oyQq8VG2ZbfZ3yR2ptdOTMvw29hqaqeycz2n66cky/+WWrVfsvPv7+ qAdaq63tLv39927Pvt1/ek/nFFxxYEz1Os24VXXaxvdmesem3viwSueq7bqVJ0PWTPD4OP8+ Z2zQoSKZPmMXx8IZG5VYijMSDbWYi4oTATqgpAA+AgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds common driver for the Top block of the Samsung Exynos SoC Low Power Audio Subsystem. This is a minimal driver which prepares resources for IP blocks like I2S, audio DMA and UART and exposes a regmap for the Top block registers. Also system power ops are added to ensure the Audio Subsystem is operational after system suspend/resume cycle. Signed-off-by: Inha Song Signed-off-by: Beomho Seo Signed-off-by: Sylwester Nawrocki Tested-by: Chanwoo Choi --- Changes since v5: - BIT() used for the register bit macro definitions, - removed unneeded dev->of_node test, - exynos_lpass_{suspend,resume} functions compiled-in conditionally, - added comments for struct exynos_lpass fields. Changes since v4: - none. Changes since v3: - moved from sound/soc/samsung and rewritten as a MFD driver, - PMU register definitions moved to include/linux/mfd/syscon/exynos5-pmu.h, - added regmap for LPASS Top SFR region, - cleaned up register bit field defintions. Changes since v2: - move misplaced SND_SAMSUNG_AUDSS Kconfig symbol addition to this patch. --- drivers/mfd/Kconfig | 8 ++ drivers/mfd/Makefile | 1 + drivers/mfd/exynos-lpass.c | 187 +++++++++++++++++++++++++++++++++ include/linux/mfd/syscon/exynos5-pmu.h | 4 +- 4 files changed, 199 insertions(+), 1 deletion(-) create mode 100644 drivers/mfd/exynos-lpass.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 2d1fb64..a7ec890 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -281,6 +281,14 @@ config MFD_DLN2 etc. must be enabled in order to use the functionality of the device. +config MFD_EXYNOS_LPASS + tristate "Samsung Exynos SoC Low Power Audio Subsystem" + select MFD_CORE + select REGMAP_MMIO + help + Select this option to enable support for Samsung Exynos Low Power + Audio Subsystem. + config MFD_MC13XXX tristate depends on (SPI_MASTER || I2C) diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 2ba3ba3..41510bb 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o obj-$(CONFIG_MFD_CROS_EC) += cros_ec.o obj-$(CONFIG_MFD_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_MFD_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_MFD_EXYNOS_LPASS) += exynos-lpass.o rtsx_pci-objs := rtsx_pcr.o rts5209.o rts5229.o rtl8411.o rts5227.o rts5249.o obj-$(CONFIG_MFD_RTSX_PCI) += rtsx_pci.o diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c new file mode 100644 index 0000000..578ac7b --- /dev/null +++ b/drivers/mfd/exynos-lpass.c @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd. + * + * Authors: Inha Song + * Sylwester Nawrocki + * + * Samsung Exynos SoC series Low Power Audio Subsystem driver. + * + * This module provides regmap for the Top SFR region and instantiates + * devices for IP blocks like DMAC, I2S, UART. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* LPASS Top register definitions */ +#define SFR_LPASS_CORE_SW_RESET 0x08 +#define LPASS_SB_SW_RESET BIT(11) +#define LPASS_UART_SW_RESET BIT(10) +#define LPASS_PCM_SW_RESET BIT(9) +#define LPASS_I2S_SW_RESET BIT(8) +#define LPASS_WDT1_SW_RESET BIT(4) +#define LPASS_WDT0_SW_RESET BIT(3) +#define LPASS_TIMER_SW_RESET BIT(2) +#define LPASS_MEM_SW_RESET BIT(1) +#define LPASS_DMA_SW_RESET BIT(0) + +#define SFR_LPASS_INTR_CA5_MASK 0x48 +#define SFR_LPASS_INTR_CPU_MASK 0x58 +#define LPASS_INTR_APM BIT(9) +#define LPASS_INTR_MIF BIT(8) +#define LPASS_INTR_TIMER BIT(7) +#define LPASS_INTR_DMA BIT(6) +#define LPASS_INTR_GPIO BIT(5) +#define LPASS_INTR_I2S BIT(4) +#define LPASS_INTR_PCM BIT(3) +#define LPASS_INTR_SLIMBUS BIT(2) +#define LPASS_INTR_UART BIT(1) +#define LPASS_INTR_SFR BIT(0) + +struct exynos_lpass { + /* pointer to the Power Management Unit regmap */ + struct regmap *pmu; + /* pointer to the LPASS TOP regmap */ + struct regmap *top; +}; + +static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask) +{ + unsigned int val = 0; + + regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val); + + val &= ~mask; + regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); + + usleep_range(100, 150); + + val |= mask; + regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); +} + +static void exynos_lpass_enable(struct exynos_lpass *lpass) +{ + /* Unmask SFR, DMA and I2S interrupt */ + regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, + LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); + + regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, + LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); + + /* Activate related PADs from retention state */ + regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, + EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR); + + exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET); + exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET); + exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET); +} + +static void exynos_lpass_disable(struct exynos_lpass *lpass) +{ + /* Mask any unmasked IP interrupt sources */ + regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0); + regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0); + + /* Deactivate related PADs from retention state */ + regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, 0); +} + +static const struct regmap_config exynos_lpass_reg_conf = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xfc, + .fast_io = true, +}; + +static int exynos_lpass_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct exynos_lpass *lpass; + void __iomem *base_top; + struct resource *res; + + lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL); + if (!lpass) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base_top = devm_ioremap_resource(dev, res); + if (IS_ERR(base_top)) + return PTR_ERR(base_top); + + lpass->top = regmap_init_mmio(dev, base_top, + &exynos_lpass_reg_conf); + if (IS_ERR(lpass->top)) { + dev_err(dev, "LPASS top regmap initialization failed\n"); + return PTR_ERR(lpass->top); + } + + lpass->pmu = syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,pmu-syscon"); + if (IS_ERR(lpass->pmu)) { + dev_err(dev, "Failed to lookup PMU regmap\n"); + return PTR_ERR(lpass->pmu); + } + + platform_set_drvdata(pdev, lpass); + exynos_lpass_enable(lpass); + + return of_platform_populate(dev->of_node, NULL, NULL, dev); +} + +#ifdef CONFIG_PM_SLEEP +static int exynos_lpass_suspend(struct device *dev) +{ + struct exynos_lpass *lpass = dev_get_drvdata(dev); + + exynos_lpass_disable(lpass); + + return 0; +} + +static int exynos_lpass_resume(struct device *dev) +{ + struct exynos_lpass *lpass = dev_get_drvdata(dev); + + exynos_lpass_enable(lpass); + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend, + exynos_lpass_resume); + +static const struct of_device_id exynos_lpass_of_match[] = { + { .compatible = "samsung,exynos5433-lpass" }, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos_lpass_of_match); + +static struct platform_driver exynos_lpass_driver = { + .driver = { + .name = "exynos-lpass", + .pm = &lpass_pm_ops, + .of_match_table = exynos_lpass_of_match, + }, + .probe = exynos_lpass_probe, +}; +module_platform_driver(exynos_lpass_driver); + +MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h index 76f30f9..c28ff21 100644 --- a/include/linux/mfd/syscon/exynos5-pmu.h +++ b/include/linux/mfd/syscon/exynos5-pmu.h @@ -43,8 +43,10 @@ #define EXYNOS5433_MIPI_PHY2_CONTROL (0x718) #define EXYNOS5_PHY_ENABLE BIT(0) - #define EXYNOS5_MIPI_PHY_S_RESETN BIT(1) #define EXYNOS5_MIPI_PHY_M_RESETN BIT(2) +#define EXYNOS5433_PAD_RETENTION_AUD_OPTION (0x3028) +#define EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR BIT(28) + #endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */