From patchwork Mon Aug 22 09:48:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 9293351 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 45C5A608A7 for ; Mon, 22 Aug 2016 09:49:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3181528830 for ; Mon, 22 Aug 2016 09:49:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 262AE287E4; Mon, 22 Aug 2016 09:49:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by 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epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id A4.24.05218.87ACAB75; Mon, 22 Aug 2016 18:48:40 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OCB00BJV1X4ZV40@mmp1.samsung.com>; Mon, 22 Aug 2016 18:48:40 +0900 (KST) From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: mturquette@baylibre.com, sboyd@codeaurora.org, kgene@kernel.org, k.kozlowski@samsung.com, chanwoo@kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chanwoo Choi Subject: [PATCH 2/5] clk: samsung: exynos3250: Fix the checkpatch warnings Date: Mon, 22 Aug 2016 18:48:36 +0900 Message-id: <1471859319-30681-3-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1471859319-30681-1-git-send-email-cw00.choi@samsung.com> References: <1471859319-30681-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNLMWRmVeSWpSXmKPExsWyRsSkULfy1K5wg3t3mS0m3rjCYnH9y3NW i9cvDC36H79mttj0+Bqrxceee6wWl3fNYbOYcX4fk8XFU64Wh9+0s1r8ONPNYrFq1x9GBx6P 9zda2T0u9/UyeeycdZfdY9OqTjaPzUvqPfq2rGL0+LxJLoA9issmJTUnsyy1SN8ugSvj9O1/ LAWzzCp6dl9ga2BcoNvFyMkhIWAicb39AzOELSZx4d56ti5GLg4hgRWMEqv3dTPDFF1c9ZAJ IrGUUeLCgg0sEM4XRomvNy6wgVSxCWhJ7H9xA8jm4BARMJS4eUgJJMwssIBJomMTO4gtLOAl cXwPRDmLgKrEzb3fweK8Aq4SrfPusEIsk5P4sOcRWJxTwE1i87lrLCC2EFDN/IbpzCB7JQRO sUs8PHSbHWKQgMS3yYdYQPZKCMhKbDoAdbSkxMEVN1gmMAovYGRYxSiaWpBcUJyUXmSkV5yY W1yal66XnJ+7iREYJ6f/PevbwXjzgPUhRgEORiUe3oyDu8KFWBPLiitzDzGaAm2YyCwlmpwP jMa8knhDYzMjC1MTU2Mjc0szJXHeBKmfwUIC6YklqdmpqQWpRfFFpTmpxYcYmTg4pRoYPTz4 Hspu4jCM+vr9wFbj/Mb7lXtuh2gLfU+7bbztm31m2McP+dnB8hyF/3r0Mjs93X9+51ywNL8z PHFOYc0U1mpZnVd/c55K56iEil56Yz//QIFq49wTm1PZO/rY/gu7JM5UCZyycIGQt0reRK0i sUV8XD/VH91kMnidf6c2y/nCLMmbZYZKLMUZiYZazEXFiQDxvjTrjgIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrBIsWRmVeSWpSXmKPExsVy+t9jAd2KU7vCDZaetrKYeOMKi8X1L89Z LV6/MLTof/ya2WLT42usFh977rFaXN41h81ixvl9TBYXT7laHH7Tzmrx40w3i8WqXX8YHXg8 3t9oZfe43NfL5LFz1l12j02rOtk8Ni+p9+jbsorR4/MmuQD2qAZGm4zUxJTUIoXUvOT8lMy8 dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zBygO5UUyhJzSoFCAYnFxUr6dpgmhIa4 6VrANEbo+oYEwfUYGaCBhDWMGadv/2MpmGVW0bP7AlsD4wLdLkZODgkBE4mLqx4yQdhiEhfu rWfrYuTiEBJYyihxYcEGFgjnC6PE1xsX2ECq2AS0JPa/uAFkc3CICBhK3DykBBJmFljAJNGx iR3EFhbwkji+B6KcRUBV4ube72BxXgFXidZ5d1ghlslJfNjzCCzOKeAmsfncNRYQWwioZn7D dOYJjLwLGBlWMUqkFiQXFCel5xrmpZbrFSfmFpfmpesl5+duYgTH4jOpHYwHd7kfYhTgYFTi 4ZU4titciDWxrLgy9xCjBAezkgiv1EmgEG9KYmVValF+fFFpTmrxIUZToMMmMkuJJucD00Re SbyhsYmZkaWRuaGFkbG5kjjv4//rwoQE0hNLUrNTUwtSi2D6mDg4pRoY019vufTw+RO7u9vd K794SBQ121ala6VElpjc+dx2r3Vp2aWKntg/3zdpKihLN2m9Pb3pYdet4/zG11uCbd884Vdf zMzTpLYnZuNUjlcLdNNsHX7PXupZtkhj+sNjr99t9naapdGi8uvSHb/IA/FGKWI9QkI+UmtX 7ZLoWGmQH/aXWzYmXHOxEktxRqKhFnNRcSIAM4g6StsCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch fixes the following warnings by using checkpatch.pl script. - Fix line 80 over characters - Remove the space prohibited after that open parenthesis '(' Signed-off-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos3250.c | 97 ++++++++++++++++++++---------------- 1 file changed, 53 insertions(+), 44 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index 1b81e283f605..cda6a85dbf9d 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -258,28 +258,38 @@ static const struct samsung_mux_clock mux_clks[] __initconst = { /* SRC_TOP0 */ MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1), - MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1), - MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1), - MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1), - MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1), - MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1), - MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1), + MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p, + SRC_TOP0, 24, 1), + MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, + SRC_TOP0, 20, 1), + MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, + SRC_TOP0, 16, 1), + MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, + SRC_TOP0, 14, 1), + MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, + SRC_TOP0, 13, 1), + MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, + SRC_TOP0, 12, 1), MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1), - MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1), + MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, + SRC_TOP0, 4, 1), MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1), /* SRC_TOP1 */ MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1), - MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p, - SRC_TOP1, 24, 1), - MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1), + MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", + mout_aclk_400_mcuisp_sub_p, SRC_TOP1, 24, 1), + MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, + SRC_TOP1, 20, 1), MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1), - MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1), + MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", + group_div_mpll_pre_p, SRC_TOP1, 8, 1), MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), /* SRC_CAM */ MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4), - MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4), + MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, + SRC_CAM, 0, 4), /* SRC_MFC */ MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), @@ -670,23 +680,23 @@ static const struct samsung_gate_clock gate_clks[] __initconst = { /* APLL & MPLL & BPLL & UPLL */ static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = { - PLL_35XX_RATE(1200000000, 400, 4, 1), - PLL_35XX_RATE(1100000000, 275, 3, 1), - PLL_35XX_RATE(1066000000, 533, 6, 1), - PLL_35XX_RATE(1000000000, 250, 3, 1), - PLL_35XX_RATE( 960000000, 320, 4, 1), - PLL_35XX_RATE( 900000000, 300, 4, 1), - PLL_35XX_RATE( 850000000, 425, 6, 1), - PLL_35XX_RATE( 800000000, 200, 3, 1), - PLL_35XX_RATE( 700000000, 175, 3, 1), - PLL_35XX_RATE( 667000000, 667, 12, 1), - PLL_35XX_RATE( 600000000, 400, 4, 2), - PLL_35XX_RATE( 533000000, 533, 6, 2), - PLL_35XX_RATE( 520000000, 260, 3, 2), - PLL_35XX_RATE( 500000000, 250, 3, 2), - PLL_35XX_RATE( 400000000, 200, 3, 2), - PLL_35XX_RATE( 200000000, 200, 3, 3), - PLL_35XX_RATE( 100000000, 200, 3, 4), + PLL_35XX_RATE(1200000000, 400, 4, 1), + PLL_35XX_RATE(1100000000, 275, 3, 1), + PLL_35XX_RATE(1066000000, 533, 6, 1), + PLL_35XX_RATE(1000000000, 250, 3, 1), + PLL_35XX_RATE(960000000, 320, 4, 1), + PLL_35XX_RATE(900000000, 300, 4, 1), + PLL_35XX_RATE(850000000, 425, 6, 1), + PLL_35XX_RATE(800000000, 200, 3, 1), + PLL_35XX_RATE(700000000, 175, 3, 1), + PLL_35XX_RATE(667000000, 667, 12, 1), + PLL_35XX_RATE(600000000, 400, 4, 2), + PLL_35XX_RATE(533000000, 533, 6, 2), + PLL_35XX_RATE(520000000, 260, 3, 2), + PLL_35XX_RATE(500000000, 250, 3, 2), + PLL_35XX_RATE(400000000, 200, 3, 2), + PLL_35XX_RATE(200000000, 200, 3, 3), + PLL_35XX_RATE(100000000, 200, 3, 4), { /* sentinel */ } }; @@ -696,16 +706,16 @@ static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = PLL_36XX_RATE(288000000, 96, 2, 2, 0), PLL_36XX_RATE(192000000, 128, 2, 3, 0), PLL_36XX_RATE(144000000, 96, 2, 3, 0), - PLL_36XX_RATE( 96000000, 128, 2, 4, 0), - PLL_36XX_RATE( 84000000, 112, 2, 4, 0), - PLL_36XX_RATE( 80000004, 106, 2, 4, 43691), - PLL_36XX_RATE( 73728000, 98, 2, 4, 19923), - PLL_36XX_RATE( 67737598, 270, 3, 5, 62285), - PLL_36XX_RATE( 65535999, 174, 2, 5, 49982), - PLL_36XX_RATE( 50000000, 200, 3, 5, 0), - PLL_36XX_RATE( 49152002, 131, 2, 5, 4719), - PLL_36XX_RATE( 48000000, 128, 2, 5, 0), - PLL_36XX_RATE( 45158401, 180, 3, 5, 41524), + PLL_36XX_RATE(96000000, 128, 2, 4, 0), + PLL_36XX_RATE(84000000, 112, 2, 4, 0), + PLL_36XX_RATE(80000004, 106, 2, 4, 43691), + PLL_36XX_RATE(73728000, 98, 2, 4, 19923), + PLL_36XX_RATE(67737598, 270, 3, 5, 62285), + PLL_36XX_RATE(65535999, 174, 2, 5, 49982), + PLL_36XX_RATE(50000000, 200, 3, 5, 0), + PLL_36XX_RATE(49152002, 131, 2, 5, 4719), + PLL_36XX_RATE(48000000, 128, 2, 5, 0), + PLL_36XX_RATE(45158401, 180, 3, 5, 41524), { /* sentinel */ } }; @@ -733,10 +743,10 @@ static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = PLL_36XX_RATE(148500000, 99, 2, 3, 0), PLL_36XX_RATE(148352005, 98, 2, 3, 59070), PLL_36XX_RATE(108000000, 144, 2, 4, 0), - PLL_36XX_RATE( 74250000, 99, 2, 4, 0), - PLL_36XX_RATE( 74176002, 98, 3, 4, 59070), - PLL_36XX_RATE( 54054000, 216, 3, 5, 14156), - PLL_36XX_RATE( 54000000, 144, 2, 5, 0), + PLL_36XX_RATE(74250000, 99, 2, 4, 0), + PLL_36XX_RATE(74176002, 98, 3, 4, 59070), + PLL_36XX_RATE(54054000, 216, 3, 5, 14156), + PLL_36XX_RATE(54000000, 144, 2, 5, 0), { /* sentinel */ } }; @@ -1098,4 +1108,3 @@ static int __init exynos3250_cmu_platform_init(void) exynos3250_cmu_isp_probe); } subsys_initcall(exynos3250_cmu_platform_init); -