From patchwork Fri Apr 21 17:19:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 9693411 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5EF586038E for ; Fri, 21 Apr 2017 18:34:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 54AA828655 for ; Fri, 21 Apr 2017 18:34:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4957128654; Fri, 21 Apr 2017 18:34:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C11FD2865B for ; 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Sat, 22 Apr 2017 02:20:23 +0900 (KST) Received: from epcpsbgm1new.samsung.com (u26.gpu120.samsung.co.kr [203.254.230.26]) by epcas1p3.samsung.com (KnoxPortal) with ESMTP id 20170421172023epcas1p3dd7397c8c61daa548ffac88a76e53113~3eVijs2Ez0428404284epcas1p3p; Fri, 21 Apr 2017 17:20:23 +0000 (GMT) X-AuditID: b6c32a37-f79f46d000003503-10-58fa3f57f4ff Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id B8.59.05715.65F3AF85; Sat, 22 Apr 2017 02:20:23 +0900 (KST) Received: from AMDC3061.digital.local ([106.116.147.40]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OOR00KJBS560G40@mmp1.samsung.com>; Sat, 22 Apr 2017 02:20:22 +0900 (KST) From: Sylwester Nawrocki To: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, alsa-devel@alsa-project.org, devicetree@vger.kernel.org Cc: inki.dae@samsung.com, sw0312.kim@samsung.com, cw00.choi@samsung.com, javier@osg.samsung.com, krzk@kernel.org, jy0922.shim@samsung.com, broonie@kernel.org, robh+dt@kernel.org, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH RFC 2/7] clk: samsung: Add definitions of some audio related clocks Date: Fri, 21 Apr 2017 19:19:46 +0200 Message-id: <1492795191-31298-3-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1492795191-31298-1-git-send-email-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAAzWSfUhTURjGd3Y/Ha0uU+wwS3IRkjDNkryRaKuoK0lI9CEW2MqLSm6uXZWM CGnkxzI3XIktUItIM0EznZNMdH5MEdSRTpSaWoYafuJEGCFtu/bf85z3977veQ6HRCQeVEpm qXNZrVqZLcNFqKX3qFx+I8GTcqxwO5Aed9iE9KeqJox+OTeP05PuBYyu6RvB6PGtNZyumDGi 9PJKo5BedDlQenS0maA3ylwYXTXaJaSffu0j6N7lYq81LeFn9jHNm09wpqWhFGdmntmFTKvh B8GUtzYAZrMlNBlPFcWls9lZ+aw2Kv62KNM8VYRpVkMfGEwWpBB8keoBSUIqBg6uH9KDAK8M hmOuJlwPRKSEsgL4vboG8KZYCFf+dgCeioE7G/UoX6gDUDdSgfDGA+Bnczvuo3AqGj7vL/e3 B1HVADotRv9ghNoBsHLMRPioQOoadM9ZUZ9GqSOwpLXLr8XUBbg50YPw+0Lh0IAJ8102gLoI Hb8J3xxIWQjYXteB8yEOwpbuXfw8dP4yELwOhH/srbs6BDbsTAv5XgOAg406wJsqb9Jio5Cn TsNeuwPzaYTaC1e3yjB+gRiWFEl4hIHd7fW7b6GAWz2dBB/fDKCxtAcxggO1QNAAglkNp8pg uWjNiUhOqeLy1BmRd3NULcD/IyJiraB5JMkGKBLI9ogFhCdFginzuQKVDUASkQWJL0V5j8Tp yoKHrDYnTZuXzXI2EEKisv3i4CZnioTKUOay91hWw2r/V4VkgLQQvLVPLUjNbQrR45u3PqyZ elLDq0Ok7+VT31a253X9G86PQ0mXewVTQe61k3jb2QTrzPrwlfBR2cT93HNvYiSTww51zlL6 7ICuEl9UD1yNkzPKBYVLP1sL8hNj35ULHGjAq+P7ZJ1pIOJ62PQL6eCdsLnDia9/Srl4a7Li 0Sm3DOUyldERiJZT/gOuevZxDQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprFIsWRmVeSWpSXmKPExsVy+t9jAd1w+18RBjcmsFhcuXiIyWLjjPWs FlMfPmGzuP7lOavF/CPnWC2ufH3PZjHpPlDJm7drmCxe3LvIYnH+/AZ2i48991gtZpzfx2TR uvcIu8XhN+1A7uSXbA78Hhs+N7F5bFrVyeZxv/s4k8eW/rvsHn1bVjF6fN4kF8AW5WaTkZqY klqkkJqXnJ+SmZduqxQa4qZroaSQl5ibaqsUoesbEqSkUJaYUwrkGRmgAQfnAPdgJX27BLeM WTfbWAveyVX0T97G3MC4W6qLkZNDQsBE4t/HFSwQtpjEhXvr2boYuTiEBJYySiz+84odJCEk 8ItR4tv/ZBCbTcBQovdoHyNIkYjAPEaJDSfXgjnMAv8YJY419YONEhYIlfjycAeYzSKgKtGx ZR+YzSvgJvH56kFmiHVyEiePTWbtYuTg4BRwl7j4FGqZm8TS/susExh5FzAyrGKUSC1ILihO Ss81zEst1ytOzC0uzUvXS87P3cQIjpdnUjsYD+5yP8QowMGoxMO7guVXhBBrYllxZe4hRgkO ZiURXm99oBBvSmJlVWpRfnxRaU5q8SFGU6C7JjJLiSbnA2M5ryTe0MTcxNzYwMLc0tLESEmc t3H2s3AhgfTEktTs1NSC1CKYPiYOTqkGxmm3El2tg2a6yL3/37Hrl0J2aMGyiLkv/GdLWlbf 8vn0fnr4zstrk64815LaJh/1WC8sd4rlrV/x//9fXXK89utzp2sTlddbPXXYe/339+yiWSmn H3ySbt4a3Vrx5+j2Le5+8R8vNkZfTg2wNV52NTTaa9mcTh/DXyaPONq3bnZT+qSf85pf+7QS S3FGoqEWc1FxIgDiOqsOrQIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170421172023epcas1p3dd7397c8c61daa548ffac88a76e53113 X-Msg-Generator: CA X-Sender-IP: 203.254.230.26 X-Local-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?= X-Global-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G1NhbXN1bmcgRWxlY3Ryb25pY3MbU2VuaW9yIFNvZnR3YXJlIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 101P X-HopCount: 7 X-CMS-RootMailID: 20170421172023epcas1p3dd7397c8c61daa548ffac88a76e53113 X-RootMTR: 20170421172023epcas1p3dd7397c8c61daa548ffac88a76e53113 References: <1492795191-31298-1-git-send-email-s.nawrocki@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds missing definitions of mux clocks required for using EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs. Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5420.c | 13 ++++++++----- include/dt-bindings/clock/exynos5420.h | 3 +++ 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index cdc092a..87c711a 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -477,8 +477,7 @@ static void __init exynos5420_clk_sleep_init(void) {} "mout_sclk_mpll", "ff_dout_spll2", "mout_sclk_spll", "mout_sclk_epll"}; PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", - "mout_sclk_mpll", - "ff_dout_spll2" }; + "mout_sclk_mpll", "ff_dout_spll2" }; PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; @@ -487,6 +486,7 @@ static void __init exynos5420_clk_sleep_init(void) {} PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; +PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock @@ -536,8 +536,8 @@ static void __init exynos5420_clk_sleep_init(void) {} MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), - MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7, - 20, 2), + MUX(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, + SRC_TOP7, 20, 2), MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), @@ -546,6 +546,8 @@ static void __init exynos5420_clk_sleep_init(void) {} MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), + MUX(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, + SRC_TOP9, 8, 1), MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, SRC_TOP9, 16, 1), MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, @@ -703,7 +705,7 @@ static void __init exynos5420_clk_sleep_init(void) {} MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), - MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1), + MUX(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1), MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), @@ -1399,6 +1401,7 @@ static void __init exynos5x_clk_init(struct device_node *np, if (_get_rate("fin_pll") == 24 * MHZ) { exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[epll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; } diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 6fd21c2..2740ae0 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -217,6 +217,9 @@ #define CLK_MOUT_MCLK_CDREX 654 #define CLK_MOUT_BPLL 655 #define CLK_MOUT_MX_MSPLL_CCORE 656 +#define CLK_MOUT_EPLL 657 +#define CLK_MOUT_MAU_EPLL 658 +#define CLK_MOUT_USER_MAU_EPLL 659 /* divider clocks */ #define CLK_DOUT_PIXEL 768