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Fri, 9 Jun 2017 10:38:49 +0000 (GMT) X-AuditID: b6c32a2e-f79506d0000046c0-5c-593a7ab97e7c Received: from epmmp2 ( [203.254.227.17]) by epsmgms2p2.samsung.com (Symantec Messaging Gateway) with SMTP id 70.F1.02294.8BA7A395; Fri, 9 Jun 2017 19:38:49 +0900 (KST) Received: from AMDC3061.digital.local ([106.116.147.40]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0ORA004HJ0897X10@mmp2.samsung.com>; Fri, 09 Jun 2017 19:38:48 +0900 (KST) From: Sylwester Nawrocki To: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: cw00.choi@samsung.com, krzk@kernel.org, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH v2 1/3] clk: samsung: Add enable/disable operation for PLL36XX clocks Date: Fri, 09 Jun 2017 12:38:29 +0200 Message-id: <1497004711-24052-1-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHIsWRmVeSWpSXmKPExsWy7bCmpu7OKqtIg1u/zCw2zljPanH9y3NW i/PnN7BbfOy5x2ox4/w+JovDb9pZHdg8Nq3qZPPo27KK0ePzJrkA5igum5TUnMyy1CJ9uwSu jJc9+5gKDulUrG5OaWB8qNLFyMEhIWAiMfeZVxcjJ5ApJnHh3nq2LkYuDiGBpYwS23u2Qjmf GSUO3XjCCFFlIrH6XA8zRGIto8Td1g9QVb8YJZ6eaWcCqWITMJToPdoH1iEi4CCx69hksDiz QLHEuvfTwGxhgXCJnrdrmUFsFgFVieNzP4HFeQXcJOYvvswOsU1O4uSxyawQ9gY2idldrBBn y0psOsAMEXaROPu3lwnCFpZ4dXwLVKuURHfHLHaQ2yQE+hklTqxpZoRwZjBK3GmfANVhLXH4 +EVWiOP4JHp/P2GCWMAr0dEmBFHiIfH8/luooY4Smzpmgi0WEoiVWL/9JPsERukFjAyrGMVS C4pz01OLTQuM9YoTc4tL89L1kvNzNzGCY1FLbwfjvwXehxgFOBiVeHg5wiwjhVgTy4orcw8x SnAwK4nwFhRbRQrxpiRWVqUW5ccXleakFh9ilOZgURLn1Vh5LUJIID2xJDU7NbUgtQgmy8TB KdXAOM/lT1/u5q3zf8uGfNlnvmWuzPwL0o2v1vhMM4qNtNV/xsm2d5PsuQl32BYqHC+NmZN+ o++1xw9G66O2xjHOIerfJS+0sW5T8m7I4Vf7LCJ420T/UHr9HpfSyU8O81w8LlP71swy6EBw 99q6iJVP0u/pvv664OLVc5fOXvzMOPnEV9+6yvVHbymxFGckGmoxFxUnAgC4lq5zwQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrGLMWRmVeSWpSXmKPExsVy+t9jQd2dVVaRBmv/sVhsnLGe1eL6l+es FufPb2C3+Nhzj9Vixvl9TBaH37SzOrB5bFrVyebRt2UVo8fnTXIBzFFuNhmpiSmpRQqpecn5 KZl56bZKoSFuuhZKCnmJuam2ShG6viFBSgpliTmlQJ6RARpwcA5wD1bSt0twy3jZs4+p4JBO xermlAbGhypdjJwcEgImEqvP9TBD2GISF+6tZ+ti5OIQEljNKHHqxWNGkISQwC9Gifnzw0Bs NgFDid6jfWBxEQEHiV3HJjOB2MwCxRJve2+ygtjCAuESu4+3gdWwCKhKHJ/7CayGV8BNYv7i y+wQy+QkTh6bzDqBkXsBI8MqRq7UguLc9NxiowKjTYzAMNt2WCtgB2PTuehDjAIcjEo8vBOa LCOFWBPLiitzDzFKcDArifAWFFtFCvGmJFZWpRblxxeV5qQWH2I0BVo5kVlKNDkfGAN5JfGG JpZGJgZmZoZGBsZmSuK8EwK/RAgJpCeWpGanphakFsH0MXFwSjUwNnVNk5vS+ery/nKP1es3 GHAwnWrQ77NYqCNfE5L/RuXtA6+WXcqmL/7WTtvEKLdt/onZAn6Xq1aY7NkmdklkgndV8wyJ zadDrjd+rXtibuaYljhPS63p8KTFvofOLw57nXJpTkmz+/NVibPfSk0LapqSzVyXV7bf7sWS ikvPJ7Zvtpyz9mG/oxJLcUaioRZzUXEiAJGkBDRJAgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170609103849epcas5p397e85db2388d4d91f5a775996cb9541d X-Msg-Generator: CA X-Sender-IP: 182.195.42.80 X-Local-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?= X-Global-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G1NhbXN1bmcgRWxlY3Ryb25pY3MbU2VuaW9yIFNvZnR3YXJlIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 105P X-CMS-RootMailID: 20170609103849epcas5p397e85db2388d4d91f5a775996cb9541d X-RootMTR: 20170609103849epcas5p397e85db2388d4d91f5a775996cb9541d References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The existing enable/disable ops for PLL35XX are made more generic and used also for PLL36XX. This fixes issues in the kernel with PLL36XX PLLs when the PLL has not been already enabled by bootloader. Reviewed-by: Chanwoo Choi Tested-by: Chanwoo Choi Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski --- Changes since v1: - none drivers/clk/samsung/clk-pll.c | 87 +++++++++++++++++++++++++------------------ 1 file changed, 50 insertions(+), 37 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index db68057..037c614 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -23,6 +23,10 @@ struct samsung_clk_pll { struct clk_hw hw; void __iomem *lock_reg; void __iomem *con_reg; + /* PLL enable control bit offset in @con_reg register */ + unsigned short enable_offs; + /* PLL lock status bit offset in @con_reg register */ + unsigned short lock_offs; enum samsung_pll_type type; unsigned int rate_count; const struct samsung_pll_rate_table *rate_table; @@ -61,6 +65,34 @@ static long samsung_pll_round_rate(struct clk_hw *hw, return rate_table[i - 1].rate; } +static int samsung_pll3xxx_enable(struct clk_hw *hw) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp; + + tmp = readl_relaxed(pll->con_reg); + tmp |= BIT(pll->enable_offs); + writel_relaxed(tmp, pll->con_reg); + + /* wait lock time */ + do { + cpu_relax(); + tmp = readl_relaxed(pll->con_reg); + } while (!(tmp & BIT(pll->lock_offs))); + + return 0; +} + +static void samsung_pll3xxx_disable(struct clk_hw *hw) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp; + + tmp = readl_relaxed(pll->con_reg); + tmp &= ~BIT(pll->enable_offs); + writel_relaxed(tmp, pll->con_reg); +} + /* * PLL2126 Clock Type */ @@ -142,34 +174,6 @@ static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw, #define PLL35XX_LOCK_STAT_SHIFT (29) #define PLL35XX_ENABLE_SHIFT (31) -static int samsung_pll35xx_enable(struct clk_hw *hw) -{ - struct samsung_clk_pll *pll = to_clk_pll(hw); - u32 tmp; - - tmp = readl_relaxed(pll->con_reg); - tmp |= BIT(PLL35XX_ENABLE_SHIFT); - writel_relaxed(tmp, pll->con_reg); - - /* wait_lock_time */ - do { - cpu_relax(); - tmp = readl_relaxed(pll->con_reg); - } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT))); - - return 0; -} - -static void samsung_pll35xx_disable(struct clk_hw *hw) -{ - struct samsung_clk_pll *pll = to_clk_pll(hw); - u32 tmp; - - tmp = readl_relaxed(pll->con_reg); - tmp &= ~BIT(PLL35XX_ENABLE_SHIFT); - writel_relaxed(tmp, pll->con_reg); -} - static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -238,12 +242,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, (rate->sdiv << PLL35XX_SDIV_SHIFT); writel_relaxed(tmp, pll->con_reg); - /* wait_lock_time if enabled */ - if (tmp & BIT(PLL35XX_ENABLE_SHIFT)) { + /* Wait until the PLL is locked if it is enabled. */ + if (tmp & BIT(pll->enable_offs)) { do { cpu_relax(); tmp = readl_relaxed(pll->con_reg); - } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT))); + } while (!(tmp & BIT(pll->lock_offs))); } return 0; } @@ -252,8 +256,8 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, .recalc_rate = samsung_pll35xx_recalc_rate, .round_rate = samsung_pll_round_rate, .set_rate = samsung_pll35xx_set_rate, - .enable = samsung_pll35xx_enable, - .disable = samsung_pll35xx_disable, + .enable = samsung_pll3xxx_enable, + .disable = samsung_pll3xxx_disable, }; static const struct clk_ops samsung_pll35xx_clk_min_ops = { @@ -275,6 +279,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, #define PLL36XX_SDIV_SHIFT (0) #define PLL36XX_KDIV_SHIFT (0) #define PLL36XX_LOCK_STAT_SHIFT (29) +#define PLL36XX_ENABLE_SHIFT (31) static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -354,10 +359,12 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(pll_con1, pll->con_reg + 4); /* wait_lock_time */ - do { - cpu_relax(); - tmp = readl_relaxed(pll->con_reg); - } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT))); + if (pll_con0 & BIT(pll->enable_offs)) { + do { + cpu_relax(); + tmp = readl_relaxed(pll->con_reg); + } while (!(tmp & BIT(pll->lock_offs))); + } return 0; } @@ -366,6 +373,8 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, .recalc_rate = samsung_pll36xx_recalc_rate, .set_rate = samsung_pll36xx_set_rate, .round_rate = samsung_pll_round_rate, + .enable = samsung_pll3xxx_enable, + .disable = samsung_pll3xxx_disable, }; static const struct clk_ops samsung_pll36xx_clk_min_ops = { @@ -1287,6 +1296,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_1450x: case pll_1451x: case pll_1452x: + pll->enable_offs = PLL35XX_ENABLE_SHIFT; + pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; if (!pll->rate_table) init.ops = &samsung_pll35xx_clk_min_ops; else @@ -1305,6 +1316,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, /* clk_ops for 36xx and 2650 are similar */ case pll_36xx: case pll_2650: + pll->enable_offs = PLL36XX_ENABLE_SHIFT; + pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; if (!pll->rate_table) init.ops = &samsung_pll36xx_clk_min_ops; else