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Fri, 21 Jul 2017 16:37:09 +0000 (GMT) X-AuditID: b6c32a2c-f79e76d00000129c-fe-59722db6a3c9 Received: from epmmp2 ( [203.254.227.17]) by epsmgms2p2.samsung.com (Symantec Messaging Gateway) with SMTP id CB.0D.05071.5BD22795; Sat, 22 Jul 2017 01:37:09 +0900 (KST) Received: from AMDC3061.digital.local ([106.116.147.40]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OTG0066Z8TJ1AB0@mmp2.samsung.com>; Sat, 22 Jul 2017 01:37:09 +0900 (KST) From: Sylwester Nawrocki To: linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@codeaurora.org, cw00.choi@samsung.com, krzk@kernel.org, linux-samsung-soc@vger.kernel.org, b.zolnierkie@samsung.com, linux-kernel@vger.kernel.org, Sylwester Nawrocki Subject: [PATCH 1/3] clk: samsung: Fix mau_epll clock definition for exynos5422 Date: Fri, 21 Jul 2017 18:36:42 +0200 Message-id: <1500655004-29816-1-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrJIsWRmVeSWpSXmKPExsWy7bCmlu423aJIg/ZGPouNM9azWlz/8pzV 4vz5DewWH3vusVpc3jWHzWLG+X1MFhdPuVocftPOavHjTDeLA6fH+xut7B6X+3qZPDat6mTz 6NuyitHj8ya5ANYoLpuU1JzMstQifbsEroxtrb2MBQsFKxbO28HUwHiFr4uRk0NCwERi6fyD 7BC2mMSFe+vZuhi5OIQEljJKfDv7Asr5zCjx9MhmFpiOdXs2MUMk1jJK3O7YxQrh/GKU6OvY BlbFJmAo0Xu0jxHEFhGQlbh17CfYKGaB54wSm56sAEpwcAgLBEo0/s8EqWERUJXY8vAGK4jN K+AmcWb/RVaIbXISJ49NBlsgIXCdTeL2hAVsIL0SQEM3HWCGqHGRuPX2BVS9sMSr41ug/pGS 6O6YxQ7R288ocWJNMyOEM4NR4k77BCaIKmuJw8chtjEL8En0/n7CBLGAV6KjTQiixEPiyL4z UAscJR48PwXWKiQQK/FscyvrBEbpBYwMqxjFUguKc9NTi00LDPWKE3OLS/PS9ZLzczcxgiNY S2cH470F3ocYBTgYlXh4DViKIoVYE8uKK3MPMUpwMCuJ8G7QAQrxpiRWVqUW5ccXleakFh9i lOZgURLn1Vh5LUJIID2xJDU7NbUgtQgmy8TBKdXAKLFvce2pw3Xaad299T1ROSofV4Te0neK cNj6fMknsRdKdr3uhhwXpfNeztym9mZV9OX9Sw8JLYplcmp6GTQtybzxbjnrMzFZxWdpwd/T r859HP2nQ7+/6keXqZbAjw1yXhNKAgwX3yw92n025+3OZRLpSW+0X89N8lPo62ZfdOLpg4yv dxmZlFiKMxINtZiLihMBejAfb9wCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrALMWRmVeSWpSXmKPExsVy+t9jQd2tukWRBr836llsnLGe1eL6l+es FufPb2C3+Nhzj9Xi8q45bBYzzu9jsrh4ytXi8Jt2VosfZ7pZHDg93t9oZfe43NfL5LFpVSeb R9+WVYwenzfJBbBGudlkpCampBYppOYl56dk5qXbKoWGuOlaKCnkJeam2ipF6PqGBCkplCXm lAJ5RgZowME5wD1YSd8uwS1jW2svY8FCwYqF83YwNTBe4eti5OSQEDCRWLdnEzOELSZx4d56 ti5GLg4hgdWMEm2vDjJCOL8YJfY0HWACqWITMJToPdrHCGKLCMhK3Dr2kw3EZhZ4yigx7VAB iC0s4C9xdcc/sHoWAVWJLQ9vsILYvAJuEmf2X2SF2CYncfLYZNYJjNwLGBlWMXKlFhTnpucW GxUYbWIEhua2w1oBOxibzkUfYhTgYFTi4TVgKYoUYk0sK67MPcQowcGsJML7Tx0oxJuSWFmV WpQfX1Sak1p8iNEUaOVEZinR5Hxg3OSVxBuaWBqZGJiZGRoZGJspifNOCPwSISSQnliSmp2a WpBaBNPHxMEp1cA482KaU4vIwXtFKUt8Mt/89ns54+PKiuKj8jwlvSGb724u1/i9bMHUu7sz WYusP6pbND7Lt+EIubzf1ypYo9rs9Cu1o9MaWo9UX33zSues/zSTn9XGJUc1r5zd0uVdOrMq Ura0msdT31Vl6coP38z8tr6JEFwqy3O95Pe+M1c0A79ca9b6/8FGiaU4I9FQi7moOBEADjly aWMCAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170721163709epcas5p11c27574e84ceebbb3387ffeb3f402043 X-Msg-Generator: CA X-Sender-IP: 182.195.42.80 X-Local-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?= X-Global-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G1NhbXN1bmcgRWxlY3Ryb25pY3MbU2VuaW9yIFNvZnR3YXJlIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 105P X-CMS-RootMailID: 20170721163709epcas5p11c27574e84ceebbb3387ffeb3f402043 X-RootMTR: 20170721163709epcas5p11c27574e84ceebbb3387ffeb3f402043 References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Parent clock of the MAU_EPLL gate clock on exynos5422 is "mout_user_mau_epll", not "mout_mau_epll_clk". This change only affects exynos5422/5800. Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5420.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 9a6476a..5ae9364 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -590,6 +590,8 @@ static void __init exynos5420_clk_sleep_init(void) {} GATE_BUS_TOP, 24, 0, 0), GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), + GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", + SRC_MASK_TOP7, 20, 0, 0), }; static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { @@ -629,6 +631,11 @@ static void __init exynos5420_clk_sleep_init(void) {} "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), }; +static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { + GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", + SRC_MASK_TOP7, 20, 0, 0), +}; + static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, SRC_TOP7, 4, 1), @@ -1001,9 +1008,6 @@ static void __init exynos5420_clk_sleep_init(void) {} GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), - GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", - SRC_MASK_TOP7, 20, 0, 0), - /* sclk */ GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), @@ -1440,6 +1444,8 @@ static void __init exynos5x_clk_init(struct device_node *np, ARRAY_SIZE(exynos5420_mux_clks)); samsung_clk_register_div(ctx, exynos5420_div_clks, ARRAY_SIZE(exynos5420_div_clks)); + samsung_clk_register_gate(ctx, exynos5420_gate_clks, + ARRAY_SIZE(exynos5420_gate_clks)); } else { samsung_clk_register_fixed_factor( ctx, exynos5800_fixed_factor_clks,