From patchwork Fri Jul 21 16:36:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 9857305 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 62C1360393 for ; Fri, 21 Jul 2017 16:37:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4FB5428621 for ; Fri, 21 Jul 2017 16:37:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 449C128623; Fri, 21 Jul 2017 16:37:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF31B28636 for ; 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Fri, 21 Jul 2017 16:37:51 +0000 (GMT) X-AuditID: b6c32a37-f79c96d000001a44-2e-59722ddfb2a4 Received: from epmmp2 ( [203.254.227.17]) by epsmgms2p1.samsung.com (Symantec Messaging Gateway) with SMTP id D1.BE.05076.FDD22795; Sat, 22 Jul 2017 01:37:51 +0900 (KST) Received: from AMDC3061.digital.local ([106.116.147.40]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OTG0066Z8TJ1AB0@mmp2.samsung.com>; Sat, 22 Jul 2017 01:37:51 +0900 (KST) From: Sylwester Nawrocki To: linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@codeaurora.org, cw00.choi@samsung.com, krzk@kernel.org, linux-samsung-soc@vger.kernel.org, b.zolnierkie@samsung.com, linux-kernel@vger.kernel.org, Sylwester Nawrocki Subject: [PATCH 2/3] clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks Date: Fri, 21 Jul 2017 18:36:43 +0200 Message-id: <1500655004-29816-2-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1500655004-29816-1-git-send-email-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOIsWRmVeSWpSXmKPExsWy7bCmnu593aJIg3nfDSw2zljPanH9y3NW i/PnN7BbfOy5x2pxedccNosZ5/cxWVw85Wpx+E07q8WPM90sDpwe72+0sntc7utl8ti0qpPN o2/LKkaPz5vkAlijuGxSUnMyy1KL9O0SuDJWzVvBXHCKt+LFwsWMDYxrubsYOTkkBEwkTk+8 zghhi0lcuLeerYuRi0NIYAejxO0XnUwQzmdGicmd09hgOt7OXgWVWMso8XP2SnYI5xejxJWu XewgVWwChhK9R/vA5ooIyErcOvYTbC6zwHNGiU1PVoAlhAUiJaav38IMYrMIqEr0vHwFFucV cJN4/7yPCWKdnMTJY5NZQWxOAXeJHd8vs4AMkhB4zSZxonMy0FQOIEdWYtMBZoh6F4mnc25D nSos8er4FnYIW0qi8eVDJojefkaJE2uaGSGcGYwSd9onQG2zljh8/CLYNmYBPol3X3tYIRbw SnS0CUGUeEi0TtgBVe4o0bXyMTQsZjFKHLu7nX0Co8wCRoZVjGKpBcW56anFhgXGesWJucWl eel6yfm5mxjB0a1lvoNxwzmfQ4wCHIxKPLwGLEWRQqyJZcWVuYcYJTiYlUR4/6kDhXhTEiur Uovy44tKc1KLDzFKc7AoifOKrb8WISSQnliSmp2aWpBaBJNl4uCUamDU/fE3528j/9mANetF 6roqtMXYvHXZrloej0u5+Y1ZeT3Dtv+pWSGzJyv+5M1k/Gd9/9rmzsgvUsfZFLKdbxotmdQd UqfZssRN1qGSNUZo1oOjNhteLbnlrH9I3ZX3g5CDbcR1ux+Ml1K6WgK8dp+rvzp9pVWGy9wv vQ8O7G7al7f0xqK1gl1KLMUZiYZazEXFiQCQnU8x6gIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBLMWRmVeSWpSXmKPExsVy+t9jQd37ukWRBpduyVtsnLGe1eL6l+es FufPb2C3+Nhzj9Xi8q45bBYzzu9jsrh4ytXi8Jt2VosfZ7pZHDg93t9oZfe43NfL5LFpVSeb R9+WVYwenzfJBbBGudlkpCampBYppOYl56dk5qXbKoWGuOlaKCnkJeam2ipF6PqGBCkplCXm lAJ5RgZowME5wD1YSd8uwS1j1bwVzAWneCteLFzM2MC4lruLkZNDQsBE4u3sVUwQtpjEhXvr 2boYuTiEBFYzSky7+AXK+cUo8fBkDytIFZuAoUTv0T5GEFtEQFbi1rGfbCA2s8BToI5DBSC2 sECkxPT1W5hBbBYBVYmel6/A6nkF3CTeP++D2iYncfLYZLCZnALuEju+X2YBsYWAalYdX8Y0 gZF3ASPDKkau1ILi3PTcYqMCw02MwFDedljLfwfjj7PRhxgFOBiVeHgNWIoihVgTy4orcw8x SnAwK4nw/lMHCvGmJFZWpRblxxeV5qQWH2I0BTplIrOUaHI+MM7ySuINTSyNTAzMzAyNDIzN lMR5JwR+iRASSE8sSc1OTS1ILYLpY+LglGpgLAn5Udn26s3RM7uMg65fPdRwQ3vupINrJuYI yIvVZIRUHJ7MKm1tn/GtfI/Jp78/9H50d23lZDE36J5x2vjtg1xdP6bwKxwhskzqKzd5bPZ/ sOdOdrL4ztYzU0OYYrnkcru8vpy7oP5pYv0yp3DTX0uY1kz2/vrJq8mrLqd+GVvOKYe++qA9 SizFGYmGWsxFxYkAhDp+V3sCAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170721163751epcas1p2fd6ba68507923b767c043b38249535e8 X-Msg-Generator: CA X-Sender-IP: 182.195.42.79 X-Local-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?= X-Global-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G1NhbXN1bmcgRWxlY3Ryb25pY3MbU2VuaW9yIFNvZnR3YXJlIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 101P X-CMS-RootMailID: 20170721163751epcas1p2fd6ba68507923b767c043b38249535e8 X-RootMTR: 20170721163751epcas1p2fd6ba68507923b767c043b38249535e8 References: <1500655004-29816-1-git-send-email-s.nawrocki@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This allows clk rate propagation up to the clock tree so EPLL can be reprogrammed indirectly when setting rate of the Audio Subsystem clocks. The advantage is that sound machine driver can operate only on the leaf clocks rather than explicitly re-configuring the root clock (EPLL). Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos-audss.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 1fab56f..b117783 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -180,7 +180,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) } clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), - CLK_SET_RATE_NO_REPARENT, + CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); cdclk = devm_clk_get(&pdev->dev, "cdclk"); @@ -195,11 +195,11 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(NULL, "dout_srp", - "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4, - 0, &lock); + "mout_audss", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, - "dout_aud_bus", "dout_srp", 0, + "dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(NULL, "dout_i2s",