From patchwork Fri Dec 13 12:59:00 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 3340191 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B61B8C0D4A for ; Fri, 13 Dec 2013 12:59:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5E458207B8 for ; Fri, 13 Dec 2013 12:59:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2625D20794 for ; Fri, 13 Dec 2013 12:59:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752141Ab3LMM7R (ORCPT ); Fri, 13 Dec 2013 07:59:17 -0500 Received: from gloria.sntech.de ([95.129.55.99]:38400 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751849Ab3LMM7Q (ORCPT ); Fri, 13 Dec 2013 07:59:16 -0500 Received: from 146-52-37-199-dynip.superkabel.de ([146.52.37.199] helo=marty.localnet) by gloria.sntech.de with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1VrSKb-0006gy-Ty; Fri, 13 Dec 2013 13:59:02 +0100 From: Heiko =?utf-8?q?St=C3=BCbner?= To: Kukjin Kim Subject: [PATCH 02/12] dt-bindings: document s3c24xx controller for external clock output Date: Fri, 13 Dec 2013 13:59:00 +0100 User-Agent: KMail/1.13.7 (Linux/3.2.0-3-686-pae; KDE/4.8.4; i686; ; ) Cc: t.figa@samsung.com, mturquette@linaro.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , devicetree@vger.kernel.org References: <201312131356.40755.heiko@sntech.de> In-Reply-To: <201312131356.40755.heiko@sntech.de> MIME-Version: 1.0 Message-Id: <201312131359.00450.heiko@sntech.de> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The clock settings are distributed over a regular register and parts of the misccr register. Signed-off-by: Heiko Stuebner --- .../bindings/clock/samsung,s3c2410-dclk.txt | 53 ++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c2410-dclk.txt diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2410-dclk.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2410-dclk.txt new file mode 100644 index 0000000..0a1f7b1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,s3c2410-dclk.txt @@ -0,0 +1,53 @@ +* Samsung S3C24XX External Clock Output Controller + +The S3C24XX series can generate clock signals on two clock output pads. +The clock binding described here is applicable to all SoCs in +the s3c24x family. + +Required Properties: + +- compatible: should be one of the following. + - "samsung,s3c2410-dclk" - controller in S3C2410 SoCs. + - "samsung,s3c2412-dclk" - controller in S3C2412 SoCs. + - "samsung,s3c2440-dclk" - controller in S3C2440 and S3C2442 SoCs. + - "samsung,s3c2443-dclk" - controller in S3C2443 and later SoCs. +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- samsung,misccr: phandle to the syscon managing the misccr register, which + holds configuration settings for different soc-components (clocks, usb, ...). + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/samsung,s3c2410-dclk.h header and can be used in device +tree sources. + +To enable the clock outputs it is necessary to configure the pins accordingly +using the pinctrl framework. + +Example: + +&pinctrl_0 { + clkout0: clkout0 { + samsung,pins = "gph-9"; + samsung,pin-function = <2>; + }; + clkout1: clkout1 { + samsung,pins = "gph-10"; + samsung,pin-function = <2>; + }; +}; + +[...] + + clocks: clock-controller@56000084 { + compatible = "samsung,s3c2410-dclk"; + reg = <0x56000084 0x4>; + #clock-cells = <1>; + samsung,misccr = <&misccr>; + + pinctrl-names = "default"; + pinctrl-0 = <&clkout0>, <&clkout1>; + };