diff mbox

[4/8] PCI: exynos: Reorder accessor functions

Message ID 20161007163554.25314.62435.stgit@bhelgaas-glaptop2.roam.corp.google.com (mailing list archive)
State Not Applicable
Headers show

Commit Message

Bjorn Helgaas Oct. 7, 2016, 4:35 p.m. UTC 
Reorder the accessors so the reader is first, as most other drivers do.  No
functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 drivers/pci/host/pci-exynos.c |   18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)


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diff mbox

Patch

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index c7b0809..5f54ab5 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -102,19 +102,14 @@  struct exynos_pcie {
 #define PCIE_PHY_TRSV3_PD_TSV		(0x1 << 7)
 #define PCIE_PHY_TRSV3_LVCC		0x31c
 
-static void exynos_elb_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
-{
-	writel(val, exynos->elbi_base + reg);
-}
-
 static u32 exynos_elb_readl(struct exynos_pcie *exynos, u32 reg)
 {
 	return readl(exynos->elbi_base + reg);
 }
 
-static void exynos_phy_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
+static void exynos_elb_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
 {
-	writel(val, exynos->phy_base + reg);
+	writel(val, exynos->elbi_base + reg);
 }
 
 static u32 exynos_phy_readl(struct exynos_pcie *exynos, u32 reg)
@@ -122,9 +117,9 @@  static u32 exynos_phy_readl(struct exynos_pcie *exynos, u32 reg)
 	return readl(exynos->phy_base + reg);
 }
 
-static void exynos_blk_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
+static void exynos_phy_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
 {
-	writel(val, exynos->block_base + reg);
+	writel(val, exynos->phy_base + reg);
 }
 
 static u32 exynos_blk_readl(struct exynos_pcie *exynos, u32 reg)
@@ -132,6 +127,11 @@  static u32 exynos_blk_readl(struct exynos_pcie *exynos, u32 reg)
 	return readl(exynos->block_base + reg);
 }
 
+static void exynos_blk_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
+{
+	writel(val, exynos->block_base + reg);
+}
+
 static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *exynos, bool on)
 {
 	u32 val;