From patchwork Wed Oct 25 14:57:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamil Konieczny X-Patchwork-Id: 10026821 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E574960381 for ; Wed, 25 Oct 2017 14:58:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC5A428BC3 for ; Wed, 25 Oct 2017 14:58:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CF91E28BDB; Wed, 25 Oct 2017 14:58:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UPPERCASE_50_75 autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1317528BC3 for ; Wed, 25 Oct 2017 14:58:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751821AbdJYO6K (ORCPT ); Wed, 25 Oct 2017 10:58:10 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:34378 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751637AbdJYO6I (ORCPT ); Wed, 25 Oct 2017 10:58:08 -0400 Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20171025145806euoutp02847d03df09a76bd7157f21b740d2955b~w2Bsj8beu0707607076euoutp029; Wed, 25 Oct 2017 14:58:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20171025145806euoutp02847d03df09a76bd7157f21b740d2955b~w2Bsj8beu0707607076euoutp029 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1508943486; bh=jikk83WkwGPEpS0tvY5Ei/aauu46rEKth/7eT4ynqO0=; h=From:To:Cc:Subject:Date:In-reply-to:References:From; b=IxXUTsxAfQEWSQcwMurEuaPALFmErswrk9T0AHonqyDusJk5o1yMl3EGNGEIdzOxj cE+Sez82ssr1VqxJ4EE+hcDa8RrmWXhvs5LJVTgm0kQe4j2p9Sfm+RNDv2tuGnbNZX AAT7RyK0W3CTtmTak1bmmszILcK/ESsLrhWvbCj8= Received: from eusmges3.samsung.com (unknown [203.254.199.242]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20171025145805eucas1p2b325b3fc14c427fb85a57281c3306c2f~w2Br2Etm52860728607eucas1p2r; Wed, 25 Oct 2017 14:58:05 +0000 (GMT) Received: from eucas1p1.samsung.com ( [182.198.249.206]) by eusmges3.samsung.com (EUCPMTA) with SMTP id 07.BA.12867.D76A0F95; Wed, 25 Oct 2017 15:58:05 +0100 (BST) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20171025145804eucas1p1743f8f5ccbe30ea6ea60210c685e8dce~w2BrK2U3r3076930769eucas1p1v; Wed, 25 Oct 2017 14:58:04 +0000 (GMT) X-AuditID: cbfec7f2-f793b6d000003243-9c-59f0a67def9f Received: from eusync2.samsung.com ( [203.254.199.212]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id AF.8D.20118.C76A0F95; Wed, 25 Oct 2017 15:58:04 +0100 (BST) Received: from AMDC3218.DIGITAL.local ([106.120.51.18]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OYD00JE0W8D4800@eusync2.samsung.com>; Wed, 25 Oct 2017 15:58:04 +0100 (BST) From: Kamil Konieczny To: k.konieczny@partner.samsung.com Cc: Herbert Xu , Krzysztof Kozlowski , Vladimir Zapolskiy , Vladimir Zapolskiy , "David S. Miller" , Bartlomiej Zolnierkiewicz , linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] crypto: s5p-sss: Change spaces to tabs Date: Wed, 25 Oct 2017 16:57:45 +0200 Message-id: <20171025145746.9712-2-k.konieczny@partner.samsung.com> X-Mailer: git-send-email 2.14.1.536.g6867272d5b56 In-reply-to: <20171025145746.9712-1-k.konieczny@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBIsWRmVeSWpSXmKPExsWy7djPc7q1yz5EGryZxmuxccZ6Vos551tY LLpfyVj07fvPaHH+/AZ2i8u75rBZzDi/j8ni2YFtbBb/fzUzO3B6bFl5k8lj2wFVj02rOtk8 dn9tYvT4t3AKi8fBd3uYPPq2rGL0+LxJLoAjissmJTUnsyy1SN8ugSvjw6TXTAVL3Ssu7L/A 0sD4xbyLkZNDQsBE4u7u52wQtpjEhXvrgWwuDiGBpYwSJ77eZ4dwPjNK7P3QwwzTsf3EW6iq ZYwSbadfM0I4/xkl1vx+wQpSxSZgLvFo+xkmEFtEQFli8r3pzCBFzAKXmCSet3eCjRIWsJZ4 v2YNWAOLgKrE5a1tLCA2r4CzxPcmiEESAoYSBzfOZgSxOQVcJNaemw22WkJgC5vEu4O/oIpc JCYveAT1hbDEq+Nb2CFsGYnLk7tZIBr6GSWW3zjFDuFMYZQ4Pu0qE0SVtcTh4xfBJjEL8ElM 2gZyKwdQnFeio00IosRD4vK0M9AAcJRoW/gMGjLTGSV2HXnHOoFRegEjwypGkdTS4tz01GJj veLE3OLSvHS95PzcTYzA+D797/inHYxfT1gdYhTgYFTi4RWY/j5SiDWxrLgy9xCjBAezkggv R+mHSCHelMTKqtSi/Pii0pzU4kOM0hwsSuK8tlFtkUIC6YklqdmpqQWpRTBZJg5OqQbGkxG3 QqYs9xUyTQqOXx15Oz94svb/yaKv6juzPIqfmsdrMouXVBZ/maYwRTah300hY6GN1t9Pu/8u 0+Ku1zr4JWOZxFzD1r6dM866cdUzh1yRWLTk3WGRbw4c/cf4/yx3a7iYXrCN/cvh3GWcdZuM 5y7/tHrFzq1VJr5d3mKiMmduMgpHrN6kxFKckWioxVxUnAgAz2d4dusCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrFLMWRmVeSWpSXmKPExsVy+t/xK7o1yz5EGkzdqGOxccZ6Vos551tY LLpfyVj07fvPaHH+/AZ2i8u75rBZzDi/j8ni2YFtbBb/fzUzO3B6bFl5k8lj2wFVj02rOtk8 dn9tYvT4t3AKi8fBd3uYPPq2rGL0+LxJLoAjissmJTUnsyy1SN8ugSvjw6TXTAVL3Ssu7L/A 0sD4xbyLkZNDQsBEYvuJt2wQtpjEhXvrgWwuDiGBJYwSO5fMYodwGpkk5u6aCFbFJmAu8Wj7 GSYQW0RAWWLyvenMIEXMAleYJL51PWIESQgLWEu8X7OGFcRmEVCVuLy1jQXE5hVwlvje9IIV Yp2hxMGNs8HqOQVcJNaemw20gANom7PE62M5Exh5FzAyrGIUSS0tzk3PLTbSK07MLS7NS9dL zs/dxAgMwW3Hfm7Zwdj1LvgQowAHoxIPr8D095FCrIllxZW5hxglOJiVRHg5Sj9ECvGmJFZW pRblxxeV5qQWH2KU5mBREuft3bM6UkggPbEkNTs1tSC1CCbLxMEp1cDY9OBgyueNn7JVt8jH lFRdbhF/9EZrY7DaQ2lOl74vC88vrfyjqL3nfVV1g+/aBbPecIkx9aTFVsqdEe68vr6EgyVx 8mqh12xJuw/MX7na9VGjaPjp8BPu3MvPyrx6xLU1sEZRmzPLgtVia+dyBfHH0uxs7ll6+UZ9 P14eCGEWmP4z+M3l/ZuUWIozEg21mIuKEwEQu0GOPQIAAA== X-CMS-MailID: 20171025145804eucas1p1743f8f5ccbe30ea6ea60210c685e8dce X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20171025145804eucas1p1743f8f5ccbe30ea6ea60210c685e8dce X-RootMTR: 20171025145804eucas1p1743f8f5ccbe30ea6ea60210c685e8dce References: <20171025145746.9712-1-k.konieczny@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Change #define lines to use tabs consistently. Acked-by: Vladimir Zapolskiy Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kamil Konieczny --- drivers/crypto/s5p-sss.c | 190 +++++++++++++++++++++++------------------------ 1 file changed, 95 insertions(+), 95 deletions(-) diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c index 7ac657f46d15..dfae1865c384 100644 --- a/drivers/crypto/s5p-sss.c +++ b/drivers/crypto/s5p-sss.c @@ -30,98 +30,98 @@ #include #include -#define _SBF(s, v) ((v) << (s)) +#define _SBF(s, v) ((v) << (s)) /* Feed control registers */ -#define SSS_REG_FCINTSTAT 0x0000 -#define SSS_FCINTSTAT_BRDMAINT BIT(3) -#define SSS_FCINTSTAT_BTDMAINT BIT(2) -#define SSS_FCINTSTAT_HRDMAINT BIT(1) -#define SSS_FCINTSTAT_PKDMAINT BIT(0) - -#define SSS_REG_FCINTENSET 0x0004 -#define SSS_FCINTENSET_BRDMAINTENSET BIT(3) -#define SSS_FCINTENSET_BTDMAINTENSET BIT(2) -#define SSS_FCINTENSET_HRDMAINTENSET BIT(1) -#define SSS_FCINTENSET_PKDMAINTENSET BIT(0) - -#define SSS_REG_FCINTENCLR 0x0008 -#define SSS_FCINTENCLR_BRDMAINTENCLR BIT(3) -#define SSS_FCINTENCLR_BTDMAINTENCLR BIT(2) -#define SSS_FCINTENCLR_HRDMAINTENCLR BIT(1) -#define SSS_FCINTENCLR_PKDMAINTENCLR BIT(0) - -#define SSS_REG_FCINTPEND 0x000C -#define SSS_FCINTPEND_BRDMAINTP BIT(3) -#define SSS_FCINTPEND_BTDMAINTP BIT(2) -#define SSS_FCINTPEND_HRDMAINTP BIT(1) -#define SSS_FCINTPEND_PKDMAINTP BIT(0) - -#define SSS_REG_FCFIFOSTAT 0x0010 -#define SSS_FCFIFOSTAT_BRFIFOFUL BIT(7) -#define SSS_FCFIFOSTAT_BRFIFOEMP BIT(6) -#define SSS_FCFIFOSTAT_BTFIFOFUL BIT(5) -#define SSS_FCFIFOSTAT_BTFIFOEMP BIT(4) -#define SSS_FCFIFOSTAT_HRFIFOFUL BIT(3) -#define SSS_FCFIFOSTAT_HRFIFOEMP BIT(2) -#define SSS_FCFIFOSTAT_PKFIFOFUL BIT(1) -#define SSS_FCFIFOSTAT_PKFIFOEMP BIT(0) - -#define SSS_REG_FCFIFOCTRL 0x0014 -#define SSS_FCFIFOCTRL_DESSEL BIT(2) -#define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00) -#define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01) -#define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02) - -#define SSS_REG_FCBRDMAS 0x0020 -#define SSS_REG_FCBRDMAL 0x0024 -#define SSS_REG_FCBRDMAC 0x0028 -#define SSS_FCBRDMAC_BYTESWAP BIT(1) -#define SSS_FCBRDMAC_FLUSH BIT(0) - -#define SSS_REG_FCBTDMAS 0x0030 -#define SSS_REG_FCBTDMAL 0x0034 -#define SSS_REG_FCBTDMAC 0x0038 -#define SSS_FCBTDMAC_BYTESWAP BIT(1) -#define SSS_FCBTDMAC_FLUSH BIT(0) - -#define SSS_REG_FCHRDMAS 0x0040 -#define SSS_REG_FCHRDMAL 0x0044 -#define SSS_REG_FCHRDMAC 0x0048 -#define SSS_FCHRDMAC_BYTESWAP BIT(1) -#define SSS_FCHRDMAC_FLUSH BIT(0) - -#define SSS_REG_FCPKDMAS 0x0050 -#define SSS_REG_FCPKDMAL 0x0054 -#define SSS_REG_FCPKDMAC 0x0058 -#define SSS_FCPKDMAC_BYTESWAP BIT(3) -#define SSS_FCPKDMAC_DESCEND BIT(2) -#define SSS_FCPKDMAC_TRANSMIT BIT(1) -#define SSS_FCPKDMAC_FLUSH BIT(0) - -#define SSS_REG_FCPKDMAO 0x005C +#define SSS_REG_FCINTSTAT 0x0000 +#define SSS_FCINTSTAT_BRDMAINT BIT(3) +#define SSS_FCINTSTAT_BTDMAINT BIT(2) +#define SSS_FCINTSTAT_HRDMAINT BIT(1) +#define SSS_FCINTSTAT_PKDMAINT BIT(0) + +#define SSS_REG_FCINTENSET 0x0004 +#define SSS_FCINTENSET_BRDMAINTENSET BIT(3) +#define SSS_FCINTENSET_BTDMAINTENSET BIT(2) +#define SSS_FCINTENSET_HRDMAINTENSET BIT(1) +#define SSS_FCINTENSET_PKDMAINTENSET BIT(0) + +#define SSS_REG_FCINTENCLR 0x0008 +#define SSS_FCINTENCLR_BRDMAINTENCLR BIT(3) +#define SSS_FCINTENCLR_BTDMAINTENCLR BIT(2) +#define SSS_FCINTENCLR_HRDMAINTENCLR BIT(1) +#define SSS_FCINTENCLR_PKDMAINTENCLR BIT(0) + +#define SSS_REG_FCINTPEND 0x000C +#define SSS_FCINTPEND_BRDMAINTP BIT(3) +#define SSS_FCINTPEND_BTDMAINTP BIT(2) +#define SSS_FCINTPEND_HRDMAINTP BIT(1) +#define SSS_FCINTPEND_PKDMAINTP BIT(0) + +#define SSS_REG_FCFIFOSTAT 0x0010 +#define SSS_FCFIFOSTAT_BRFIFOFUL BIT(7) +#define SSS_FCFIFOSTAT_BRFIFOEMP BIT(6) +#define SSS_FCFIFOSTAT_BTFIFOFUL BIT(5) +#define SSS_FCFIFOSTAT_BTFIFOEMP BIT(4) +#define SSS_FCFIFOSTAT_HRFIFOFUL BIT(3) +#define SSS_FCFIFOSTAT_HRFIFOEMP BIT(2) +#define SSS_FCFIFOSTAT_PKFIFOFUL BIT(1) +#define SSS_FCFIFOSTAT_PKFIFOEMP BIT(0) + +#define SSS_REG_FCFIFOCTRL 0x0014 +#define SSS_FCFIFOCTRL_DESSEL BIT(2) +#define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00) +#define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01) +#define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02) + +#define SSS_REG_FCBRDMAS 0x0020 +#define SSS_REG_FCBRDMAL 0x0024 +#define SSS_REG_FCBRDMAC 0x0028 +#define SSS_FCBRDMAC_BYTESWAP BIT(1) +#define SSS_FCBRDMAC_FLUSH BIT(0) + +#define SSS_REG_FCBTDMAS 0x0030 +#define SSS_REG_FCBTDMAL 0x0034 +#define SSS_REG_FCBTDMAC 0x0038 +#define SSS_FCBTDMAC_BYTESWAP BIT(1) +#define SSS_FCBTDMAC_FLUSH BIT(0) + +#define SSS_REG_FCHRDMAS 0x0040 +#define SSS_REG_FCHRDMAL 0x0044 +#define SSS_REG_FCHRDMAC 0x0048 +#define SSS_FCHRDMAC_BYTESWAP BIT(1) +#define SSS_FCHRDMAC_FLUSH BIT(0) + +#define SSS_REG_FCPKDMAS 0x0050 +#define SSS_REG_FCPKDMAL 0x0054 +#define SSS_REG_FCPKDMAC 0x0058 +#define SSS_FCPKDMAC_BYTESWAP BIT(3) +#define SSS_FCPKDMAC_DESCEND BIT(2) +#define SSS_FCPKDMAC_TRANSMIT BIT(1) +#define SSS_FCPKDMAC_FLUSH BIT(0) + +#define SSS_REG_FCPKDMAO 0x005C /* AES registers */ #define SSS_REG_AES_CONTROL 0x00 -#define SSS_AES_BYTESWAP_DI BIT(11) -#define SSS_AES_BYTESWAP_DO BIT(10) -#define SSS_AES_BYTESWAP_IV BIT(9) -#define SSS_AES_BYTESWAP_CNT BIT(8) -#define SSS_AES_BYTESWAP_KEY BIT(7) -#define SSS_AES_KEY_CHANGE_MODE BIT(6) -#define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00) -#define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01) -#define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02) -#define SSS_AES_FIFO_MODE BIT(3) -#define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00) -#define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01) -#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02) -#define SSS_AES_MODE_DECRYPT BIT(0) +#define SSS_AES_BYTESWAP_DI BIT(11) +#define SSS_AES_BYTESWAP_DO BIT(10) +#define SSS_AES_BYTESWAP_IV BIT(9) +#define SSS_AES_BYTESWAP_CNT BIT(8) +#define SSS_AES_BYTESWAP_KEY BIT(7) +#define SSS_AES_KEY_CHANGE_MODE BIT(6) +#define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00) +#define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01) +#define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02) +#define SSS_AES_FIFO_MODE BIT(3) +#define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00) +#define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01) +#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02) +#define SSS_AES_MODE_DECRYPT BIT(0) #define SSS_REG_AES_STATUS 0x04 -#define SSS_AES_BUSY BIT(2) -#define SSS_AES_INPUT_READY BIT(1) -#define SSS_AES_OUTPUT_READY BIT(0) +#define SSS_AES_BUSY BIT(2) +#define SSS_AES_INPUT_READY BIT(1) +#define SSS_AES_OUTPUT_READY BIT(0) #define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2)) #define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2)) @@ -129,22 +129,22 @@ #define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2)) #define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2)) -#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg)) -#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg)) -#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg)) +#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg)) +#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg)) +#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg)) -#define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg) +#define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg) #define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \ SSS_AES_REG(dev, reg)) /* HW engine modes */ -#define FLAGS_AES_DECRYPT BIT(0) -#define FLAGS_AES_MODE_MASK _SBF(1, 0x03) -#define FLAGS_AES_CBC _SBF(1, 0x01) -#define FLAGS_AES_CTR _SBF(1, 0x02) +#define FLAGS_AES_DECRYPT BIT(0) +#define FLAGS_AES_MODE_MASK _SBF(1, 0x03) +#define FLAGS_AES_CBC _SBF(1, 0x01) +#define FLAGS_AES_CTR _SBF(1, 0x02) -#define AES_KEY_LEN 16 -#define CRYPTO_QUEUE_LEN 1 +#define AES_KEY_LEN 16 +#define CRYPTO_QUEUE_LEN 1 /** * struct samsung_aes_variant - platform specific SSS driver data