From patchwork Fri Dec 22 16:48:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lukasz Stelmach X-Patchwork-Id: 10130947 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0D0D060318 for ; Fri, 22 Dec 2017 16:49:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B4F029BCE for ; Fri, 22 Dec 2017 16:49:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F42132A0C7; Fri, 22 Dec 2017 16:49:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8303F29BCE for ; Fri, 22 Dec 2017 16:49:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755971AbdLVQsr (ORCPT ); Fri, 22 Dec 2017 11:48:47 -0500 Received: from mailout1.w1.samsung.com ([210.118.77.11]:58131 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753456AbdLVQsp (ORCPT ); Fri, 22 Dec 2017 11:48:45 -0500 Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id 20171222164842euoutp01f94a97958cdc54f91a169de7a7397102~Cq81CD_j13079430794euoutp01H; Fri, 22 Dec 2017 16:48:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com 20171222164842euoutp01f94a97958cdc54f91a169de7a7397102~Cq81CD_j13079430794euoutp01H DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1513961322; bh=JrzorLcbxKs0v5fA43cOpqDtMq42GHk/rRmwNE9DHu8=; h=From:To:Cc:Subject:Date:In-reply-to:References:From; b=UTLkiyk+ios+SmCYtf0rfb4UdYFFur7kLoPysw/DspfcHSE7PLLwupqzegxu/vyWy sr1O0Z0R+eMqFrAK8O5Qoratj/cUKJQd2G0jXcdBN4+mrOkrvWJbVa/EQuShjzSdaY L1MmBgBHrNXsXIbdKqo77JEQIgFMC6suVUEoqlhg= Received: from eusmges2.samsung.com (unknown [203.254.199.241]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20171222164841eucas1p21f83843dd39c0cfbc4fef75f01048ca6~Cq8zsKnMp2402724027eucas1p2x; Fri, 22 Dec 2017 16:48:41 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges2.samsung.com (EUCPMTA) with SMTP id FE.57.12907.9673D3A5; Fri, 22 Dec 2017 16:48:41 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20171222164840eucas1p17e3d17666ba3d0c5fced2d1c9259bf0b~Cq8yotUoG0229702297eucas1p1N; Fri, 22 Dec 2017 16:48:40 +0000 (GMT) X-AuditID: cbfec7f1-f793a6d00000326b-1b-5a3d3769f9c5 Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id B8.6C.18832.8673D3A5; Fri, 22 Dec 2017 16:48:40 +0000 (GMT) MIME-version: 1.0 Content-transfer-encoding: 8BIT Content-type: text/plain; charset="UTF-8" Received: from localhost ([106.116.147.110]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P1D00E5ZG13KP20@eusync1.samsung.com>; Fri, 22 Dec 2017 16:48:40 +0000 (GMT) From: =?UTF-8?q?=C5=81ukasz=20Stelmach?= To: Philippe Ombredanne , "Andrew F . Davis" , PrasannaKumar Muralidharan , Rob Herring , Matt Mackall , Herbert Xu , Krzysztof Kozlowski , Kukjin Kim , devicetree@vger.kernel.org, linux-crypto@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?=C5=81ukasz=20Stelmach?= , Marek Szyprowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v5] hwrng: exynos - add Samsung Exynos True RNG driver Date: Fri, 22 Dec 2017 17:48:35 +0100 Message-id: <20171222164835.1051-1-l.stelmach@samsung.com> X-Mailer: git-send-email 2.11.0 In-reply-to: <20171222132338.30054-1-l.stelmach@samsung.com> Organization: Samsung R&D Institute Poland X-Brightmail-Tracker: H4sIAAAAAAAAA02SbUhTURjHObu7L0rT25Q6maSM/KCQvaB1sxkKKvdTWd9akI28TNGpbSrZ l6bgdGbON8xEUDNfGtOp6XSWpnNtltUye5NwhaMiXa0ysWVm266S337n/J///zzPwyEQvhkN ItKzchlZljhTgPly9WaXdV/6kVjRgdZhjHI+qsKp3nodSjWZnqLU1YVgSm1fRCirtQenZo2d gHpnc3GomeFGjKq3jnKoLtMcTjXrKwC1vuo2tKktgCoeMeFx/rShYQ6n9WNhdJ9GhdEdhii6 ol8D6IrPPYC2vBnk0Et9e5IJka8wlclMz2dk+4+f900zP3FgOR8TL1W3TWAK0Hm0DPgQkIyC s71TGMs74DObzs2+BJ9sA/DrvI7DHpYAXNaugk2H3VwKWKEdwJabL3GPwCO3w181Nm4ZIAiE DIGm5xmea4QMhwN3dThb/xPAEduINwgj46G6bRL1CIHkOAK/NNdxPQfEkzquf+htKoBMgrbl fi9zyTDomn6/8VoMHNLVIWxLIXBYOY162IcUwnnVB2+9PxkBtUWvvaGQbMdhj72SwxoS4MzK bZTlALhg6cdZDoaq0nEOa1ADONG0siHUAtjaEsfyMfhHU4Wxw/nBav11xDMzJHmwVMlnkYaz ilNsdTy8ZRhB2fHdkQanA6sEIQ1bNtbwf2MNWzbWDBANCGTy5FIJIz8UKRdL5XlZksgL2dI+ 4P5dU38t34eAczLGCEgCCLbxmgWxIj4qzpcXSI0AEoggkJc/KRTxeanigsuMLDtFlpfJyI1g N8EV7OTFipRn+KREnMtkMEwOI9tUOYRPkAIkraiKSrr70d/XpJa1K33d0Wc1PavJQ/PKi9NK V0JN4q4XrwxpJ+7diCstCSjeG7xGKu4fXvn04NtCYhEeLsqNKGwsacxuKT9t9esgarsiLa3z oaa3A1p6PWdsXDhR6LgDTg6WO5YXJc7UyejcUbvISmib4qdCiqpCz/1I6Xos4MrTxAcjEJlc /A8VwshpWQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprNIsWRmVeSWpSXmKPExsVy+t/xy7oZ5rZRBl2/OS3en5rIbrFxxnpW i/lHzrFadL+Sseh//JrZ4vz5DewWNw+tYLS4f+8nk8XlXXPYLGac38dksfbIXXaLBdv6GC3+ /wZqWNp/nNGide8Rdgd+j52z7rJ7bDug6rFpVSebx/KdJh59W1YxevS93MDocfzGdiaPz5vk AjiiuGxSUnMyy1KL9O0SuDKOnX3DVvDMtWLS0sNsDYwrLLsYOTkkBEwkHh/rYISwxSQu3FvP 1sXIxSEksIRRovVQPxtIgldAUOLH5HssXYwcHMwC8hJHLmWDhJkF1CUmzVvEDFH/jVHix8TD 7CAJNgFHif6lJ1hBEiICh5klZt24ADaVWWAZo8SfnlawqcICbhL3vm4Bs1kEVCV+XnzADrHN SmLH+mnMECfJS+xqu8gKYnMK2Eg86nwKVi8kYC3RfWAJmM0voCWxpuk6ywRGwVlIjp2FcOws JMcuYGRexSiSWlqcm55bbKhXnJhbXJqXrpecn7uJERhl24793LyD8dLG4EOMAhyMSjy8C5Rs o4RYE8uKK3MPMUpwMCuJ8JadsIkS4k1JrKxKLcqPLyrNSS0+xCjNwaIkztu7Z3WkkEB6Yklq dmpqQWoRTJaJg1OqgdF+/ZLzERHNllbPLa/yxwufuHjnVnnfk6C1ckFrQ25/eKns3hBaVPxD asr04sSnd0ytY14u9I0P3+o84VGLxJS29zdjn24MCkqRXyu37NnH5MnnFpTMKXnTtempx8Tv L0xWPJj89Gnci66z3ropjo7/G9Z7fZz4YpLrnUjp/RybFha06eSu+P1SiaU4I9FQi7moOBEA zSu/lq4CAAA= X-CMS-MailID: 20171222164840eucas1p17e3d17666ba3d0c5fced2d1c9259bf0b X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20171222164840eucas1p17e3d17666ba3d0c5fced2d1c9259bf0b X-RootMTR: 20171222164840eucas1p17e3d17666ba3d0c5fced2d1c9259bf0b References: <20171222132338.30054-1-l.stelmach@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for True Random Number Generator found in Samsung Exynos 5250+ SoCs. Signed-off-by: Łukasz Stelmach Reviewed-by: Krzysztof Kozlowski Acked-by: Philippe Ombredanne --- Changes since v4: - SPDX license header instead of the traditional blurb. - MODULE_LICENSE("GPL v2") instead of "GPL" Thank you, Philippe Ombredanne. MAINTAINERS | 7 ++ drivers/char/hw_random/Kconfig | 12 ++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/exynos-trng.c | 237 +++++++++++++++++++++++++++++++++++ 4 files changed, 257 insertions(+) create mode 100644 drivers/char/hw_random/exynos-trng.c diff --git a/MAINTAINERS b/MAINTAINERS index e6d849d0d153..1082846edb9b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11933,6 +11933,13 @@ S: Maintained F: drivers/crypto/exynos-rng.c F: Documentation/devicetree/bindings/crypto/samsung,exynos-rng4.txt +SAMSUNG EXYNOS TRUE RANDOM NUMBER GENERATOR (TRNG) DRIVER +M: Łukasz Stelmach +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: drivers/char/hw_random/exynos-trng.c +F: Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.txt + SAMSUNG FRAMEBUFFER DRIVER M: Jingoo Han L: linux-fbdev@vger.kernel.org diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 90e4bb24819e..32f715394904 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -437,6 +437,18 @@ config HW_RANDOM_S390 If unsure, say Y. +config HW_RANDOM_EXYNOS + tristate "Samsung Exynos True Random Number Generator support" + depends on ARCH_EXYNOS || COMPILE_TEST + default HW_RANDOM + ---help--- + This driver provides support for the True Random Number + Generator available in Exynos SoCs. + + To compile this driver as a module, choose M here: the module + will be called exynos-trng. + + If unsure, say Y. endif # HW_RANDOM config UML_RANDOM diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile index e7146a84d44a..7c8a66fe8cf6 100644 --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o n2-rng-y := n2-drv.o n2-asm.o obj-$(CONFIG_HW_RANDOM_VIA) += via-rng.o +obj-$(CONFIG_HW_RANDOM_EXYNOS) += exynos-trng.o obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o obj-$(CONFIG_HW_RANDOM_OMAP3_ROM) += omap3-rom-rng.o diff --git a/drivers/char/hw_random/exynos-trng.c b/drivers/char/hw_random/exynos-trng.c new file mode 100644 index 000000000000..34d6f51ecbee --- /dev/null +++ b/drivers/char/hw_random/exynos-trng.c @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RNG driver for Exynos TRNGs + * + * Author: Łukasz Stelmach + * + * Copyright 2017 (c) Samsung Electronics Software, Inc. + * + * Based on the Exynos PRNG driver drivers/crypto/exynos-rng by + * Krzysztof Kozłowski + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EXYNOS_TRNG_CLKDIV (0x0) + +#define EXYNOS_TRNG_CTRL (0x20) +#define EXYNOS_TRNG_CTRL_RNGEN BIT(31) + +#define EXYNOS_TRNG_POST_CTRL (0x30) +#define EXYNOS_TRNG_ONLINE_CTRL (0x40) +#define EXYNOS_TRNG_ONLINE_STAT (0x44) +#define EXYNOS_TRNG_ONLINE_MAXCHI2 (0x48) +#define EXYNOS_TRNG_FIFO_CTRL (0x50) +#define EXYNOS_TRNG_FIFO_0 (0x80) +#define EXYNOS_TRNG_FIFO_1 (0x84) +#define EXYNOS_TRNG_FIFO_2 (0x88) +#define EXYNOS_TRNG_FIFO_3 (0x8c) +#define EXYNOS_TRNG_FIFO_4 (0x90) +#define EXYNOS_TRNG_FIFO_5 (0x94) +#define EXYNOS_TRNG_FIFO_6 (0x98) +#define EXYNOS_TRNG_FIFO_7 (0x9c) +#define EXYNOS_TRNG_FIFO_LEN (8) +#define EXYNOS_TRNG_CLOCK_RATE (500000) + + +struct exynos_trng_dev { + struct device *dev; + void __iomem *mem; + struct clk *clk; + struct hwrng rng; +}; + +static int exynos_trng_do_read(struct hwrng *rng, void *data, size_t max, + bool wait) +{ + struct exynos_trng_dev *trng; + u32 val; + + max = min_t(size_t, max, (EXYNOS_TRNG_FIFO_LEN * 4)); + + trng = (struct exynos_trng_dev *)rng->priv; + + writel_relaxed(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL); + val = readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val, + val == 0, 200, 1000000); + if (val < 0) + return val; + + memcpy_fromio(data, trng->mem + EXYNOS_TRNG_FIFO_0, max); + + return max; +} + +static int exynos_trng_init(struct hwrng *rng) +{ + struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv; + unsigned long sss_rate; + u32 val; + + sss_rate = clk_get_rate(trng->clk); + + /* + * For most TRNG circuits the clock frequency of under 500 kHz + * is safe. + */ + val = sss_rate / (EXYNOS_TRNG_CLOCK_RATE * 2); + if (val > 0x7fff) { + dev_err(trng->dev, "clock divider too large: %d", val); + return -ERANGE; + } + val = val << 1; + writel_relaxed(val, trng->mem + EXYNOS_TRNG_CLKDIV); + + /* Enable the generator. */ + val = EXYNOS_TRNG_CTRL_RNGEN; + writel_relaxed(val, trng->mem + EXYNOS_TRNG_CTRL); + + /* + * Disable post-processing. /dev/hwrng is supposed to deliver + * unprocessed data. + */ + writel_relaxed(0, trng->mem + EXYNOS_TRNG_POST_CTRL); + + return 0; +} + +static int exynos_trng_probe(struct platform_device *pdev) +{ + struct exynos_trng_dev *trng; + struct resource *res; + int ret = -ENOMEM; + + trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL); + if (!trng) + return ret; + + trng->rng.name = devm_kstrdup(&pdev->dev, dev_name(&pdev->dev), + GFP_KERNEL); + if (!trng->rng.name) + return ret; + + trng->rng.init = exynos_trng_init; + trng->rng.read = exynos_trng_do_read; + trng->rng.priv = (unsigned long) trng; + + platform_set_drvdata(pdev, trng); + trng->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + trng->mem = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(trng->mem)) { + dev_err(&pdev->dev, "Could not map IO resources.\n"); + return PTR_ERR(trng->mem); + } + + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_get_sync(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "Could not get runtime PM.\n"); + goto err_pm_get; + } + + trng->clk = devm_clk_get(&pdev->dev, "secss"); + if (IS_ERR(trng->clk)) { + ret = PTR_ERR(trng->clk); + dev_err(&pdev->dev, "Could not get clock.\n"); + goto err_clock; + } + + ret = clk_prepare_enable(trng->clk); + if (ret) { + dev_err(&pdev->dev, "Could not enable the clk.\n"); + goto err_clock; + } + + ret = hwrng_register(&trng->rng); + if (ret) { + dev_err(&pdev->dev, "Could not register hwrng device.\n"); + goto err_register; + } + + dev_info(&pdev->dev, "Exynos True Random Number Generator.\n"); + + return 0; + +err_register: + clk_disable_unprepare(trng->clk); + +err_clock: + pm_runtime_put_sync(&pdev->dev); + +err_pm_get: + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static int exynos_trng_remove(struct platform_device *pdev) +{ + struct exynos_trng_dev *trng = platform_get_drvdata(pdev); + + hwrng_unregister(&trng->rng); + clk_disable_unprepare(trng->clk); + + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int __maybe_unused exynos_trng_suspend(struct device *dev) +{ + pm_runtime_put_sync(dev); + + return 0; +} + +static int __maybe_unused exynos_trng_resume(struct device *dev) +{ + int ret; + + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Could not get runtime PM.\n"); + pm_runtime_put_noidle(dev); + return ret; + } + + return 0; +} + +static SIMPLE_DEV_PM_OPS(exynos_trng_pm_ops, exynos_trng_suspend, + exynos_trng_resume); + +static const struct of_device_id exynos_trng_dt_match[] = { + { + .compatible = "samsung,exynos5250-trng", + }, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos_trng_dt_match); + +static struct platform_driver exynos_trng_driver = { + .driver = { + .name = "exynos-trng", + .pm = &exynos_trng_pm_ops, + .of_match_table = exynos_trng_dt_match, + }, + .probe = exynos_trng_probe, + .remove = exynos_trng_remove, +}; + +module_platform_driver(exynos_trng_driver); +MODULE_AUTHOR("Łukasz Stelmach"); +MODULE_DESCRIPTION("H/W TRNG driver for Exynos chips"); +MODULE_LICENSE("GPL v2");