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Fri, 16 Feb 2018 14:58:07 +0000 (GMT) Received: from eucas1p1.samsung.com ( [182.198.249.206]) by eusmges1new.samsung.com (EUCPMTA) with SMTP id 16.41.05700.E71F68A5; Fri, 16 Feb 2018 14:58:06 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20180216145804eucas1p20cc58695fce84f9acc03a16b6913fcb2~T1kOF1B2B0119801198eucas1p2p; Fri, 16 Feb 2018 14:58:04 +0000 (GMT) X-AuditID: cbfec7f2-5ffe19c000011644-4d-5a86f17ed971 Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 03.60.04183.C71F68A5; Fri, 16 Feb 2018 14:58:04 +0000 (GMT) Received: from AMDC2768.DIGITAL.local ([106.120.43.17]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P49008BP08QWR80@eusync3.samsung.com>; Fri, 16 Feb 2018 14:58:04 +0000 (GMT) From: Andrzej Hajda To: Sylwester Nawrocki Cc: Andrzej Hajda , Bartlomiej Zolnierkiewicz , Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Kukjin Kim , Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org (moderated list:SAMSUNG SOC CLOCK DRIVERS), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK) Subject: [PATCH v2 2/7] clk: samsung: exynos5250: fix PLL rates Date: Fri, 16 Feb 2018 15:57:49 +0100 Message-id: <20180216145754.14428-3-a.hajda@samsung.com> X-Mailer: git-send-email 2.16.1 In-reply-to: <20180216145754.14428-1-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrHIsWRmVeSWpSXmKPExsWy7djPc7p1H9uiDE7/k7C4te4cq8XGGetZ La5/ec5q0f/4NbPF+fMb2C0+9txjtZhxfh+Txdojd9ktLp5ytTj8pp3V4t+1jSwWq3b9YXTg 8Xh/o5XdY+esu+wem1Z1snn0bVnF6PF5k1wAaxSXTUpqTmZZapG+XQJXxpvPj9kLjvNXTFi4 jb2B8TtPFyMnh4SAicS/lQvZuhi5OIQEVjBKXHu6kwnC+cwo0fh6JStM1YeFH1lAbCGBZYwS q95aQxT9Z5RYebmPDSTBJqAp8XfzTTBbREBfYsmqi2A2s0Aji8SKOWIgtrCAvcTcW5/YQWwW AVWJ803TwWxeAQuJCd2v2CGWyUscftMEtphTwFLiwuSnjCDLJARWsEms2vmdGaLIReL9kZ9Q 1wlLvDq+BapZRuLy5G4WiIZuRolT+zqZIZwpjBLnX11mgqiyljh8/CIrxHl8EpO2TQcq4gCK 80p0tAlBlHhILJ95mQXCdpSY+vUpK8TLPYwSB9/PZ5zAKLWAkWEVo3hqaXFuemqxYV5quV5x Ym5xaV66XnJ+7iZGYCyf/nf80w7Gr5eSDjEKcDAq8fA+eNwWJcSaWFZcmXuIUYKDWUmE9zlI iDclsbIqtSg/vqg0J7X4EKM0B4uSOG+cRl2UkEB6YklqdmpqQWoRTJaJg1OqgVH+5NM3Kc+D ymbve6whLfe2MrbsU98EL/5ppz79P7ey8dNTkWWOW/fK5/a5PWuozVjZGm8T45Hyw8D+yMcj AYuEzx/QMqhWO+7ifCxlgj/Xnu+dScUzN2f+0PwhtV6B50JA2JSp5gLFJscPHRXaoGln6y+j xO+W/2jR9GsF+5qKHodM6Io4V6PEUpyRaKjFXFScCAD939Ni4QIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrALMWRmVeSWpSXmKPExsVy+t/xq7o1H9uiDJb+MLS4te4cq8XGGetZ La5/ec5q0f/4NbPF+fMb2C0+9txjtZhxfh+Txdojd9ktLp5ytTj8pp3V4t+1jSwWq3b9YXTg 8Xh/o5XdY+esu+wem1Z1snn0bVnF6PF5k1wAaxSXTUpqTmZZapG+XQJXxpvPj9kLjvNXTFi4 jb2B8TtPFyMnh4SAicSHhR9Zuhi5OIQEljBKPHr2nBHCaWSSuN6yhQWkik1AU+Lv5ptsILaI gL7EklUX2UCKmAUaWSSurdrICJIQFrCXmHvrEzuIzSKgKnG+aTqYzStgITGh+xU7xDp5icNv mlhBbE4BS4kLk5+C9QoB1Zx5s5ZtAiPPAkaGVYwiqaXFuem5xUZ6xYm5xaV56XrJ+bmbGIHh tu3Yzy07GLveBR9iFOBgVOLhffC4LUqINbGsuDL3EKMEB7OSCO9zkBBvSmJlVWpRfnxRaU5q 8SFGaQ4WJXHe8waVUUIC6YklqdmpqQWpRTBZJg5OqQbGlRGb+t//2/3u3dKjW8Pl/TJ9hY+f /sE29fxS14MGfySytyTwGIlfvsGe80/4zreIov+/ZP7WmbG+KlybVB+eu/yeWj2/rhDb5K9J Ibf+CG2rP9ig07fB7u87Bb7F/wK//ND6NidSTGNNz4Nefsm5y0+zL29Zc6jgLvuPuT68N0xL IoQPbWN7qcRSnJFoqMVcVJwIAM9il+kzAgAA X-CMS-MailID: 20180216145804eucas1p20cc58695fce84f9acc03a16b6913fcb2 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180216145804eucas1p20cc58695fce84f9acc03a16b6913fcb2 X-RootMTR: 20180216145804eucas1p20cc58695fce84f9acc03a16b6913fcb2 References: <20180216145754.14428-1-a.hajda@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. If that is not the case, rate of parent might be being set not as expected. For instance, if in the PLL rates table we have a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate will return 393216003. If we now attempt to set rate of a PLL's child divider clock to 393216000/2 its rate will be 131072001, rather than 196608000. That is the divider will be set to 3 instead of 2, because 393216003/2 is greater than 196608000. To fix this issue declared rates are changed to exactly match rates generated by a PLL, as calculated from the P, M, S, K coefficients. Signed-off-by: Andrzej Hajda Acked-by: Chanwoo Choi Acked-by: Tomasz Figa --- drivers/clk/samsung/clk-exynos5250.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 9b073c98a891..923c608b1b95 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -711,13 +711,13 @@ static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ PLL_36XX_RATE(192000000, 64, 2, 2, 0), - PLL_36XX_RATE(180633600, 90, 3, 2, 20762), + PLL_36XX_RATE(180633605, 90, 3, 2, 20762), PLL_36XX_RATE(180000000, 90, 3, 2, 0), PLL_36XX_RATE(73728000, 98, 2, 4, 19923), - PLL_36XX_RATE(67737600, 90, 2, 4, 20762), + PLL_36XX_RATE(67737602, 90, 2, 4, 20762), PLL_36XX_RATE(49152000, 98, 3, 4, 19923), - PLL_36XX_RATE(45158400, 90, 3, 4, 20762), - PLL_36XX_RATE(32768000, 131, 3, 5, 4719), + PLL_36XX_RATE(45158401, 90, 3, 4, 20762), + PLL_36XX_RATE(32768001, 131, 3, 5, 4719), { }, };