| Message ID | 20180216145754.14428-4-a.hajda@samsung.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
On 2018년 02월 16일 23:57, Andrzej Hajda wrote: > Rates declared in PLL rate tables should match exactly rates calculated > from PLL coefficients. If that is not the case, rate of parent might be being > set not as expected. For instance, if in the PLL rates table we have > a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate > callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate > will return 393216003. If we now attempt to set rate of a PLL's child divider > clock to 393216000/2 its rate will be 131072001, rather than 196608000. > That is the divider will be set to 3 instead of 2, because 393216003/2 is > greater than 196608000. > > To fix this issue declared rates are changed to exactly match rates generated > by a PLL, as calculated from the P, M, S, K coefficients. > > Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> > Acked-by: Tomasz Figa <tomasz.figa@gmail.com> > --- > drivers/clk/samsung/clk-exynos5260.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c > index fd1d9bfc151b..8eae1752d700 100644 > --- a/drivers/clk/samsung/clk-exynos5260.c > +++ b/drivers/clk/samsung/clk-exynos5260.c > @@ -65,7 +65,7 @@ static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = { > PLL_36XX_RATE(480000000, 160, 2, 2, 0), > PLL_36XX_RATE(432000000, 144, 2, 2, 0), > PLL_36XX_RATE(400000000, 200, 3, 2, 0), > - PLL_36XX_RATE(394073130, 459, 7, 2, 49282), > + PLL_36XX_RATE(394073128, 459, 7, 2, 49282), > PLL_36XX_RATE(333000000, 111, 2, 2, 0), > PLL_36XX_RATE(300000000, 100, 2, 2, 0), > PLL_36XX_RATE(266000000, 266, 3, 3, 0), > Looks good to me. Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c index fd1d9bfc151b..8eae1752d700 100644 --- a/drivers/clk/samsung/clk-exynos5260.c +++ b/drivers/clk/samsung/clk-exynos5260.c @@ -65,7 +65,7 @@ static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = { PLL_36XX_RATE(480000000, 160, 2, 2, 0), PLL_36XX_RATE(432000000, 144, 2, 2, 0), PLL_36XX_RATE(400000000, 200, 3, 2, 0), - PLL_36XX_RATE(394073130, 459, 7, 2, 49282), + PLL_36XX_RATE(394073128, 459, 7, 2, 49282), PLL_36XX_RATE(333000000, 111, 2, 2, 0), PLL_36XX_RATE(300000000, 100, 2, 2, 0), PLL_36XX_RATE(266000000, 266, 3, 3, 0),