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Fri, 16 Feb 2018 14:58:09 +0000 (GMT) Received: from eucas1p1.samsung.com ( [182.198.249.206]) by eusmges2new.samsung.com (EUCPMTA) with SMTP id 24.94.17380.E71F68A5; Fri, 16 Feb 2018 14:58:07 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20180216145805eucas1p14670777cd5339fda26b95c71b726f866~T1kOpZcZy1688416884eucas1p1-; Fri, 16 Feb 2018 14:58:05 +0000 (GMT) X-AuditID: cbfec7f4-b4fc79c0000043e4-39-5a86f17e1866 Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id B8.50.04178.D71F68A5; Fri, 16 Feb 2018 14:58:05 +0000 (GMT) Received: from AMDC2768.DIGITAL.local ([106.120.43.17]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P49008BP08QWR80@eusync3.samsung.com>; Fri, 16 Feb 2018 14:58:05 +0000 (GMT) From: Andrzej Hajda To: Sylwester Nawrocki Cc: Andrzej Hajda , Bartlomiej Zolnierkiewicz , Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Kukjin Kim , Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org (moderated list:SAMSUNG SOC CLOCK DRIVERS), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK) Subject: [PATCH v2 3/7] clk: samsung: exynos5260: fix PLL rates Date: Fri, 16 Feb 2018 15:57:50 +0100 Message-id: <20180216145754.14428-4-a.hajda@samsung.com> X-Mailer: git-send-email 2.16.1 In-reply-to: <20180216145754.14428-1-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrHIsWRmVeSWpSXmKPExsWy7djPc7r1H9uiDL6UWNxad47VYuOM9awW 1788Z7Xof/ya2eL8+Q3sFh977rFazDi/j8li7ZG77BYXT7laHH7Tzmrx79pGFotVu/4wOvB4 vL/Ryu6xc9Zddo9NqzrZPPq2rGL0+LxJLoA1issmJTUnsyy1SN8ugSujeUc3a8FPnooDL4+z NzA+4+pi5OSQEDCRaD16grWLkYtDSGAFo8T/H71MEM5nRolz7TcYYaqW35rBDpFYxiix485l qKr/jBJHHnYygVSxCWhK/N18kw3EFhHQl1iy6iKYzSzQyCKxYo4YiC0sYC9xs/cMK4jNIqAq 8fZVOwuIzStgIfF873lWiG3yEoffNIHZnAKWEhcmP2UEWSYhsIJNYt+xtewQRS4SE//cg7KF JV4d3wJly0h0dhxkgmjoZpQ4ta+TGcKZwihx/tVlJogqa4nDxy+yQpzHJzFp23SgIg6gOK9E R5sQRImHxPHny6D+d5R4OOkl1P89jBK3t+1mmsAotYCRYRWjeGppcW56arFRXmq5XnFibnFp Xrpecn7uJkZgLJ/+d/zLDsZdf5IOMQpwMCrx8Fo8a4sSYk0sK67MPcQowcGsJML7/DFQiDcl sbIqtSg/vqg0J7X4EKM0B4uSOG+cRl2UkEB6YklqdmpqQWoRTJaJg1OqgVHppGb7F6tDafsn 73r5wXDX2skXtkvkfv534tfLpX+U3r2+597cLNbwa4bXp2z7Z9lHOqquLrCZYJSzSDDj3bXb 09i/FSTcic5L3m0rOduszSidi1V/+W/FGK27W+UXar3R6JW+s6LAi8F/l4r7vJe9U6udU242 aWx0dD318/oMhxsGfPV1C4KVWIozEg21mIuKEwG35sSw4QIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrALMWRmVeSWpSXmKPExsVy+t/xq7q1H9uiDD4fFLO4te4cq8XGGetZ La5/ec5q0f/4NbPF+fMb2C0+9txjtZhxfh+Txdojd9ktLp5ytTj8pp3V4t+1jSwWq3b9YXTg 8Xh/o5XdY+esu+wem1Z1snn0bVnF6PF5k1wAaxSXTUpqTmZZapG+XQJXRvOObtaCnzwVB14e Z29gfMbVxcjJISFgIrH81gz2LkYuDiGBJYwSV94tgnIamSTa226xgFSxCWhK/N18kw3EFhHQ l1iy6iIbSBGzQCOLxLVVGxlBEsIC9hI3e8+wgtgsAqoSb1+1gzXzClhIPN97nhVinbzE4TdN YDangKXEhclPwXqFgGrOvFnLNoGRZwEjwypGkdTS4tz03GJDveLE3OLSvHS95PzcTYzAcNt2 7OfmHYyXNgYfYhTgYFTi4X3wuC1KiDWxrLgy9xCjBAezkgjvc5AQb0piZVVqUX58UWlOavEh RmkOFiVx3vMGlVFCAumJJanZqakFqUUwWSYOTqkGxh6b7lXP9p38vPzldX7jv3+mX7u1V2nr n1TDibeWlpys3LGOwyUmhcWAJeLwVssTjAlPxLOT3jCv8/U5Yy4dOW+u+4UTx8xaotYsma+z ec9u75b8t+U3g3PPBS5LVn1noRu6kSeuODpnksMbRmmLD7/NiyVvrxOZ0DbjQ/40p09TVy9Q j/Rnfq7EUpyRaKjFXFScCACn7/CCMwIAAA== X-CMS-MailID: 20180216145805eucas1p14670777cd5339fda26b95c71b726f866 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180216145805eucas1p14670777cd5339fda26b95c71b726f866 X-RootMTR: 20180216145805eucas1p14670777cd5339fda26b95c71b726f866 References: <20180216145754.14428-1-a.hajda@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. If that is not the case, rate of parent might be being set not as expected. For instance, if in the PLL rates table we have a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate will return 393216003. If we now attempt to set rate of a PLL's child divider clock to 393216000/2 its rate will be 131072001, rather than 196608000. That is the divider will be set to 3 instead of 2, because 393216003/2 is greater than 196608000. To fix this issue declared rates are changed to exactly match rates generated by a PLL, as calculated from the P, M, S, K coefficients. Signed-off-by: Andrzej Hajda Acked-by: Tomasz Figa Acked-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos5260.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c index fd1d9bfc151b..8eae1752d700 100644 --- a/drivers/clk/samsung/clk-exynos5260.c +++ b/drivers/clk/samsung/clk-exynos5260.c @@ -65,7 +65,7 @@ static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = { PLL_36XX_RATE(480000000, 160, 2, 2, 0), PLL_36XX_RATE(432000000, 144, 2, 2, 0), PLL_36XX_RATE(400000000, 200, 3, 2, 0), - PLL_36XX_RATE(394073130, 459, 7, 2, 49282), + PLL_36XX_RATE(394073128, 459, 7, 2, 49282), PLL_36XX_RATE(333000000, 111, 2, 2, 0), PLL_36XX_RATE(300000000, 100, 2, 2, 0), PLL_36XX_RATE(266000000, 266, 3, 3, 0),