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Fri, 16 Feb 2018 14:58:08 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges3new.samsung.com (EUCPMTA) with SMTP id A0.D3.10409.F71F68A5; Fri, 16 Feb 2018 14:58:07 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20180216145805eucas1p28452227465bf275bb00dec65ab5b3978~T1kPHZMeS0119801198eucas1p2q; Fri, 16 Feb 2018 14:58:05 +0000 (GMT) X-AuditID: cbfec7f5-f95739c0000028a9-8e-5a86f17f511a Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 04.60.04183.D71F68A5; Fri, 16 Feb 2018 14:58:05 +0000 (GMT) Received: from AMDC2768.DIGITAL.local ([106.120.43.17]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P49008BP08QWR80@eusync3.samsung.com>; Fri, 16 Feb 2018 14:58:05 +0000 (GMT) From: Andrzej Hajda To: Sylwester Nawrocki Cc: Andrzej Hajda , Bartlomiej Zolnierkiewicz , Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Kukjin Kim , Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org (moderated list:SAMSUNG SOC CLOCK DRIVERS), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK) Subject: [PATCH v2 4/7] clk: samsung: exynos5433: fix PLL rates Date: Fri, 16 Feb 2018 15:57:51 +0100 Message-id: <20180216145754.14428-5-a.hajda@samsung.com> X-Mailer: git-send-email 2.16.1 In-reply-to: <20180216145754.14428-1-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNIsWRmVeSWpSXmKPExsWy7djP87r1H9uiDP5/FrW4te4cq8XGGetZ La5/ec5q0f/4NbPF+fMb2C0+9txjtZhxfh+Txdojd9ktLp5ytTj8pp3V4t+1jSwWq3b9YXTg 8Xh/o5XdY+esu+wem1Z1snn0bVnF6PF5k1wAaxSXTUpqTmZZapG+XQJXxs6n9gXrRSr6rrUx NTB+FOhi5OSQEDCRaF+0iK2LkYtDSGAFo8T8HV+YIZzPjBIdi5+zwlQ979kJZgsJLGOU6Dnj DVH0n1HiyMNOJpAEm4CmxN/NN9lAbBEBfYklqy6C2cwCjSwSK+aIgdjCAvYSn3uPgw1iEVCV mLn+ByOIzStgIXHzzzaoZfISh980gdmcApYSFyY/ZQRZJiGwhE1i4pxtbBBFLhLrD05ghrCF JV4d38IOYctIXJ7czQLR0M0ocWpfJzOEM4VR4vyry0wQVdYSh49fZIU4j09i0rbpQEUcQHFe iY42IYgSD4kzD3cyQYQdJT7dq4X4vodRYu02uwmMUgsYGVYxiqeWFuempxYb56WW6xUn5haX 5qXrJefnbmIERvHpf8e/7mDc9yfpEKMAB6MSD6/Fs7YoIdbEsuLK3EOMEhzMSiK8zx8DhXhT EiurUovy44tKc1KLDzFKc7AoifPGadRFCQmkJ5akZqemFqQWwWSZODilGhhTTj3cmf+o6faV Qj6J6f1Ou03lp8rVHfRxXPnMpqvprnCsqvDpc4uWi0VFOE2bwqe6jqU4MmG9zO8+rsYHtx+U FFqf/+CQw3DywNPt155ty5nlkuO6mT2d8WPchHP+WTryU1ne3Sxcsv1cy/JDMnfzeWe93Pb8 G9OuuqvSvrtZv0XZPJcR/fFCiaU4I9FQi7moOBEAt1eCQ94CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPLMWRmVeSWpSXmKPExsVy+t/xq7q1H9uiDHZvN7e4te4cq8XGGetZ La5/ec5q0f/4NbPF+fMb2C0+9txjtZhxfh+Txdojd9ktLp5ytTj8pp3V4t+1jSwWq3b9YXTg 8Xh/o5XdY+esu+wem1Z1snn0bVnF6PF5k1wAaxSXTUpqTmZZapG+XQJXxs6n9gXrRSr6rrUx NTB+FOhi5OSQEDCReN6zk7WLkYtDSGAJo8Tzz9PYIZxGJon2tlssIFVsApoSfzffZAOxRQT0 JZasusgGUsQs0MgicW3VRkaQhLCAvcTn3uOsIDaLgKrEzPU/wOK8AhYSN/9sY4VYJy9x+E0T mM0pYClxYfJTsBohoJozb9ayTWDkWcDIsIpRJLW0ODc9t9hIrzgxt7g0L10vOT93EyMw2LYd +7llB2PXu+BDjAIcjEo8vA8et0UJsSaWFVfmHmKU4GBWEuF9DhLiTUmsrEotyo8vKs1JLT7E KM3BoiTOe96gMkpIID2xJDU7NbUgtQgmy8TBKdXAeL1iU0QOZ/qhVccOHed+/OGjbMaVzacW x7BkTTDT2d3n7dgkI1Yh/6JFvuvVVVPe2idZG3XMcnZKmi/7sWBB1v5zV3S2KLI3Ws2+9/Z2 WufxdvuPR9Y8czKYsSjqTFSMyVFemR3atjk/OydUGyvmRjS0vnQx/rzE4UlU+PXKGa+DJOoO rV0fpMRSnJFoqMVcVJwIABOisnkyAgAA X-CMS-MailID: 20180216145805eucas1p28452227465bf275bb00dec65ab5b3978 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180216145805eucas1p28452227465bf275bb00dec65ab5b3978 X-RootMTR: 20180216145805eucas1p28452227465bf275bb00dec65ab5b3978 References: <20180216145754.14428-1-a.hajda@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. If that is not the case, rate of parent might be being set not as expected. For instance, if in the PLL rates table we have a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate will return 393216003. If we now attempt to set rate of a PLL's child divider clock to 393216000/2 its rate will be 131072001, rather than 196608000. That is the divider will be set to 3 instead of 2, because 393216003/2 is greater than 196608000. To fix this issue declared rates are changed to exactly match rates generated by a PLL, as calculated from the P, M, S, K coefficients. Signed-off-by: Andrzej Hajda Acked-by: Tomasz Figa Acked-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos5433.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 57a41824ee2e..7985352ceb2f 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -729,7 +729,7 @@ static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = PLL_35XX_RATE(800000000U, 400, 6, 1), PLL_35XX_RATE(733000000U, 733, 12, 1), PLL_35XX_RATE(700000000U, 175, 3, 1), - PLL_35XX_RATE(667000000U, 222, 4, 1), + PLL_35XX_RATE(666000000U, 222, 4, 1), PLL_35XX_RATE(633000000U, 211, 4, 1), PLL_35XX_RATE(600000000U, 500, 5, 2), PLL_35XX_RATE(552000000U, 460, 5, 2), @@ -757,12 +757,12 @@ static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = /* AUD_PLL */ static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = { PLL_36XX_RATE(400000000U, 200, 3, 2, 0), - PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), + PLL_36XX_RATE(393216003U, 197, 3, 2, -25690), PLL_36XX_RATE(384000000U, 128, 2, 2, 0), - PLL_36XX_RATE(368640000U, 246, 4, 2, -15729), - PLL_36XX_RATE(361507200U, 181, 3, 2, -16148), - PLL_36XX_RATE(338688000U, 113, 2, 2, -6816), - PLL_36XX_RATE(294912000U, 98, 1, 3, 19923), + PLL_36XX_RATE(368639991U, 246, 4, 2, -15729), + PLL_36XX_RATE(361507202U, 181, 3, 2, -16148), + PLL_36XX_RATE(338687988U, 113, 2, 2, -6816), + PLL_36XX_RATE(294912002U, 98, 1, 3, 19923), PLL_36XX_RATE(288000000U, 96, 1, 3, 0), PLL_36XX_RATE(252000000U, 84, 1, 3, 0), PLL_36XX_RATE(196608001U, 197, 3, 3, -25690),