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Fri, 16 Feb 2018 14:58:09 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges2new.samsung.com (EUCPMTA) with SMTP id 15.94.17380.F71F68A5; Fri, 16 Feb 2018 14:58:08 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20180216145806eucas1p1e939d3138e29d3446df90e1a69ea9624~T1kPrC1UG1688416884eucas1p1A; Fri, 16 Feb 2018 14:58:06 +0000 (GMT) X-AuditID: cbfec7f4-b4fc79c0000043e4-3d-5a86f17ffd08 Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id A9.50.04178.E71F68A5; Fri, 16 Feb 2018 14:58:06 +0000 (GMT) Received: from AMDC2768.DIGITAL.local ([106.120.43.17]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P49008BP08QWR80@eusync3.samsung.com>; Fri, 16 Feb 2018 14:58:06 +0000 (GMT) From: Andrzej Hajda To: Sylwester Nawrocki Cc: Andrzej Hajda , Bartlomiej Zolnierkiewicz , Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Kukjin Kim , Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org (moderated list:SAMSUNG SOC CLOCK DRIVERS), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK) Subject: [PATCH v2 5/7] clk: samsung: exynos7: fix PLL rates Date: Fri, 16 Feb 2018 15:57:52 +0100 Message-id: <20180216145754.14428-6-a.hajda@samsung.com> X-Mailer: git-send-email 2.16.1 In-reply-to: <20180216145754.14428-1-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrLIsWRmVeSWpSXmKPExsWy7djP87oNH9uiDHZdYLK4te4cq8XGGetZ La5/ec5q0f/4NbPF+fMb2C0+9txjtZhxfh+Txdojd9ktLp5ytTj8pp3V4t+1jSwWq3b9YXTg 8Xh/o5XdY+esu+wem1Z1snn0bVnF6PF5k1wAaxSXTUpqTmZZapG+XQJXRvfVy8wFJ7grbuyL a2A8zdnFyMkhIWAiMXXCC9YuRi4OIYEVjBK3j3UyQzifGSWePzrHBFO1/s1jNojEMkaJyes+ QVX9Z5R4cXMeC0gVm4CmxN/NN9lAbBEBfYklqy6C2cwCjSwSK+aIgdjCAjYSn7+ANHNysAio SixruAxm8wpYSKyctIgdYpu8xOE3TawgNqeApcSFyU8ZQZZJCKxgk1j78hLQSRxAjovEnMNa EPXCEq+Ob4HqlZHo7DjIBFHfzShxah/EPxICUxglzr+6DPWPtcTh4xdZIa7jk5i0bTozxFBe iY42IYgSD4kD2yEekBBwlHjy4wsTxMc9jBJTlnUzTWCUWsDIsIpRPLW0ODc9tdgoL7Vcrzgx t7g0L10vOT93EyMwkk//O/5lB+OuP0mHGAU4GJV4eC2etUUJsSaWFVfmHmKU4GBWEuF9/hgo xJuSWFmVWpQfX1Sak1p8iFGag0VJnDdOoy5KSCA9sSQ1OzW1ILUIJsvEwSnVwGi597KLIdP2 zEqzptLAoEshB7tumQnozHES2H4yvTB2OuOl1wydJu8uFtQf49X9vzNC4Xry5g4mTq8e9z0y f3ec8ZC8EhrPvtzNNHj7x2zzx6fbTGd+VJaOCXu6j435jviUVPUTO/qy/S9VNTJ/+N8peS3b VW9yZfHHtwqJ79q3e8zx+1H6S4mlOCPRUIu5qDgRANLMShTgAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHLMWRmVeSWpSXmKPExsVy+t/xq7p1H9uiDB6vk7a4te4cq8XGGetZ La5/ec5q0f/4NbPF+fMb2C0+9txjtZhxfh+Txdojd9ktLp5ytTj8pp3V4t+1jSwWq3b9YXTg 8Xh/o5XdY+esu+wem1Z1snn0bVnF6PF5k1wAaxSXTUpqTmZZapG+XQJXRvfVy8wFJ7grbuyL a2A8zdnFyMkhIWAisf7NY7YuRi4OIYEljBKHttxiAkkICTQySUw8YgFiswloSvzdfJMNxBYR 0JdYsuoiWAOzQCOLxLVVGxlBEsICNhKfv3xiBrFZBFQlljVcBrN5BSwkVk5axA6xTV7i8Jsm VhCbU8BS4sLkp4wQyywkzrxZyzaBkWcBI8MqRpHU0uLc9NxiQ73ixNzi0rx0veT83E2MwFDb duzn5h2MlzYGH2IU4GBU4uF98LgtSog1say4MvcQowQHs5II73OQEG9KYmVValF+fFFpTmrx IUZpDhYlcd7zBpVRQgLpiSWp2ampBalFMFkmDk6pBkZWrSTenoVb/T7rfzy0sYQt76GeYO4O izb2knYV6f3n3d4H91+Z+0D24tp1W7nCzOJDLViOMmpf2tC6c3dNhdiStn2vHBTEt03JE/n4 dZt28bWD+d8kT9wQlcjbcp8ldJbVlt3nY01Z2o7vOq4s6vo1XG6NjtmbhzcmJAudmM2ypuZI +Exrcx0lluKMREMt5qLiRAAaDOYpMQIAAA== X-CMS-MailID: 20180216145806eucas1p1e939d3138e29d3446df90e1a69ea9624 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180216145806eucas1p1e939d3138e29d3446df90e1a69ea9624 X-RootMTR: 20180216145806eucas1p1e939d3138e29d3446df90e1a69ea9624 References: <20180216145754.14428-1-a.hajda@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. If that is not the case, rate of parent might be being set not as expected. For instance, if in the PLL rates table we have a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate will return 393216003. If we now attempt to set rate of a PLL's child divider clock to 393216000/2 its rate will be 131072001, rather than 196608000. That is the divider will be set to 3 instead of 2, because 393216003/2 is greater than 196608000. To fix this issue declared rates are changed to exactly match rates generated by a PLL, as calculated from the P, M, S, K coefficients. Signed-off-by: Andrzej Hajda Acked-by: Tomasz Figa Acked-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 5931a4140c3d..bbfa57b4e017 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -140,7 +140,7 @@ static const struct samsung_div_clock topc_div_clks[] __initconst = { }; static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = { - PLL_36XX_RATE(491520000, 20, 1, 0, 31457), + PLL_36XX_RATE(491519897, 20, 1, 0, 31457), {}, };