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Fri, 18 Jan 2019 13:17:12 +0000 (GMT) From: Kamil Konieczny To: k.konieczny@partner.samsung.com, linux-samsung-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org, Chanwoo Choi , devicetree@vger.kernel.org, Krzysztof Kozlowski , Kukjin Kim , Mark Rutland , Rob Herring , Sylwester Nawrocki , Bartlomiej Zolnierkiewicz , Marek Szyprowski Subject: [PATCH v4 4/5] dt-bindings: clk: exynos5433: add imem clock Date: Fri, 18 Jan 2019 14:16:38 +0100 Message-Id: <20190118131639.17578-5-k.konieczny@partner.samsung.com> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190118131639.17578-1-k.konieczny@partner.samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrOKsWRmVeSWpSXmKPExsWy7djPc7o3LzrGGPzfqW+xccZ6VovrX56z Wsw/co7Vom/ff0aL/sevmS3On9/AbvGx5x6rxYzz+5gs1h65y26x9PpFJovWvUfYLQ6/aWd1 4PFYM28No8emVZ1sHgff7WHy6NuyitHj8ya5ANYoLpuU1JzMstQifbsErowPfy6xFPQKV3xo PsDcwLhcoIuRk0NCwESiYe9y5i5GLg4hgRWMEg8n3mYHSQgJfGGUWHnNGyLxmVHi7vIvjDAd U66dYIYoWs4ocWGbNUQRUMOL7y+ZQBJsAuYSj7afAbNFBNwk+ibPZgMpYhZoY5Z4OrsLLCEs 4CLxe9N9NhCbRUBV4vvMvSwgNi9Q/Pm1iSwQ2+Qlpq2GqOcUcJWYt24FK0SNoMTJmU/AapiB apq3zgb7QUJgG7vEwu07oE51kTj/7gmULSzx6vgWdghbRuL05B6oBeUSu7c+Y4dobmGUmDt5 ERNEwlri8PGLQNs4gDZoSqzfpQ8RdpQ4+eoSO0hYQoBP4sZbQYgb+CQmbZvODBHmlehoE4Ko 1pWY9/8MK4QtLdH1fx2U7SGx+WYv+wRGxVlIvpmF5JtZCHsXMDKvYhRPLS3OTU8tNspLLdcr TswtLs1L10vOz93ECExOp/8d/7KDcdefpEOMAhyMSjy8E7Y4xAixJpYVV+YeYpTgYFYS4eVa 4RgjxJuSWFmVWpQfX1Sak1p8iFGag0VJnLea4UG0kEB6YklqdmpqQWoRTJaJg1OqgTHn/s4/ r6cUxD6d47TN9eXFDd4fDia+eZiSv/JtyLHTWb1JL9nYWNxO37x+yf7e1OT7C3Lf7P0zR3ju 0v9mLaW5xXdmOD7l+Wn++cx+/vor0hOP/H4bufryd6PwWc6x/mwHZ75xmtd6wW73lZbZ4qmN 7x3fTTny0dT1lVfMEf75O4NKn7lnNKabKLEUZyQaajEXFScCAPy7njNKAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t/xu7o3LjrGGPxea2GxccZ6VovrX56z Wsw/co7Vom/ff0aL/sevmS3On9/AbvGx5x6rxYzz+5gs1h65y26x9PpFJovWvUfYLQ6/aWd1 4PFYM28No8emVZ1sHgff7WHy6NuyitHj8ya5ANYoPZui/NKSVIWM/OISW6VoQwsjPUNLCz0j E0s9Q2PzWCsjUyV9O5uU1JzMstQifbsEvYwPfy6xFPQKV3xoPsDcwLhcoIuRk0NCwERiyrUT zF2MXBxCAksZJd7P2MMGkZCWaDy9mgnCFpb4c62LDaLoE6PEr62bGEESbALmEo+2nwErEhHw kJgxcTErSBGzQB+zxOeD59lBEsICLhK/N90Hm8oioCrxfeZeFhCbFyj+/NpEFogN8hLTVneB DeIUcJWYt24FK4gtBFRzYU4HM0S9oMTJmU/A6pmB6pu3zmaewCgwC0lqFpLUAkamVYwiqaXF uem5xUZ6xYm5xaV56XrJ+bmbGIGRtO3Yzy07GLveBR9iFOBgVOLhfbHNIUaINbGsuDL3EKME B7OSCC/XCscYId6UxMqq1KL8+KLSnNTiQ4ymQE9MZJYSTc4HRnleSbyhqaG5haWhubG5sZmF kjjveYPKKCGB9MSS1OzU1ILUIpg+Jg5OqQZGPcXtn5Pins1deZPPbdZs4VWqt42jGDnFv3rH P9vDE3b086XdmX9ai7/NCWty3vBh78JFfz7khp1bUfvhqdRyRgGr74sX2stL7Wd6sMK1w396 8KLJ034k3eSMcTjCLSuwYKbvDUVDphSpt3cUDgadZHbk8BWa5K1ssCb8YGufU3qm6LqfCYyC SizFGYmGWsxFxYkA0RNoELoCAAA= X-CMS-MailID: 20190118131713eucas1p21e6deb9c80627cbf2e09c5b578cd410a X-Msg-Generator: CA X-RootMTR: 20190118131713eucas1p21e6deb9c80627cbf2e09c5b578cd410a X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190118131713eucas1p21e6deb9c80627cbf2e09c5b578cd410a References: <20190118131639.17578-1-k.konieczny@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT bindings to describe imem clocks for SSS (Security SubSystem) and SlimSSS in Exynos5433. Signed-off-by: Kamil Konieczny Reviewed-by: Rob Herring --- include/dt-bindings/clock/exynos5433.h | 55 ++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 87bb2b017143..cc6153a0b5f7 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -1406,4 +1406,59 @@ #define CAM1_NR_CLK 113 +/* CMU_IMEM */ +#define CLK_ACLK_SSS 1 +#define CLK_ACLK_SLIMSSS 2 +#define CLK_ACLK_RTIC 3 +#define CLK_ACLK_XIU_SSSX 4 +#define CLK_ACLK_ASYNCAHBM_SSS_ATLAS 5 +#define CLK_ACLK_ASYNCAXI_SSSX 6 +#define CLK_ACLK_BTS_SSS_CCI 7 +#define CLK_ACLK_BTS_SSS_DRAM 8 +#define CLK_ACLK_BTS_SLIMSSS 9 +#define CLK_ACLK_SMMU_SSS_CCI 10 +#define CLK_ACLK_SMMU_SSS_DRAM 11 +#define CLK_ACLK_SMMU_SLIMSSS 12 +#define CLK_ACLK_SMMU_RTIC 13 +#define CLK_ACLK_IMEMND_266 14 +#define CLK_ACLK_ALB_IMEM 15 +#define CLK_ACLK_XIU_IMEMX 16 +#define CLK_ACLK_AXIUS_IMEMX 17 +#define CLK_ACLK_ASYNCAXI_IMEMX 18 +#define CLK_ACLK_ARBG_TX 19 +#define CLK_ACLK_BTS_ARBG_TX 20 +#define CLK_ACLK_SMMU_ARBG_TX 21 +#define CLK_ACLK_GIC 22 +#define CLK_ACLK_INT_MEM 23 +#define CLK_ACLK_XIU_PIMEMX 24 +#define CLK_ACLK_AXI2APB_IMEM0P 25 +#define CLK_ACLK_AXI2APB_IMEM1P 26 +#define CLK_ACLK_ASYNCAXIS_MIF_PIMEMX 27 +#define CLK_ACLK_AXIDS_PIMEMX_GIC 28 +#define CLK_ACLK_AXIDS_PIMEMX_IMEM0P 29 +#define CLK_ACLK_AXIDS_PIMEMX_IMEM1P 30 +#define CLK_ACLK_SROMC 31 +#define CLK_ACLK_AXIDS_SROMC 32 +#define CLK_ACLK_AXI2AHB_IMEMH 33 +#define CLK_PCLK_SSS 34 +#define CLK_PCLK_SLIMSSS 35 +#define CLK_PCLK_RTIC 36 +#define CLK_PCLK_SYSREG_IMEM 37 +#define CLK_PCLK_PMU_IMEM 38 +#define CLK_PCLK_ALB_IMEM 39 +#define CLK_PCLK_BTS_SSS_CCI 40 +#define CLK_PCLK_BTS_SSS_DRAM 41 +#define CLK_PCLK_BTS_SLIMSSS 42 +#define CLK_PCLK_SMMU_SSS_CCI 43 +#define CLK_PCLK_SMMU_SSS_DRAM 44 +#define CLK_PCLK_SMMU_SLIMSSS 45 +#define CLK_PCLK_SMMU_RTIC 46 +#define CLK_PCLK_ASYNCAPB_ARBG_TX 47 +#define CLK_PCLK_BTS_ARBG_TX 48 +#define CLK_PCLK_SMMU_ARBG_TX 49 +#define CLK_PCLK_ASYNCAXI_IMEMX 50 +#define CLK_PCLK_GPIO_IMEM 51 + +#define IMEM_NR_CLK 52 + #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */