| Message ID | 20190828121005.29368-2-m.szyprowski@samsung.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | Exynos SoCs: enable support for ARM Architected Timers | expand |
Dear Marek, On 19. 8. 28. 오후 9:10, Marek Szyprowski wrote: > All CortexA7/A15 based Exynos5 SoCs have ARM architected timers, so enable > support for them directly in the base dtsi. None of the known firmware > properly configures CNTFRQ arch timer register, so force clock frequency > to 24MHz, which is the only configuration supported by the remaining > clock drivers so far. > > Stock firmware for Peach Pit and Pi Chromebooks also doesn't reset > properly other arch timer registers, so add respective properties > indicating that. Other Exynos5-based boards behaves correctly in this area, > what finally allows to enable support for KVM-based virtualization. > > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > --- > arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 ++++ > arch/arm/boot/dts/exynos54xx.dtsi | 9 +++++++++ > arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++++ > 3 files changed, 17 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts > index f78db6809cca..77e08a4c7300 100644 > --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts > +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts > @@ -1064,6 +1064,10 @@ > status = "okay"; > }; > > +&timer { > + arm,cpu-registers-not-fw-configured; > +}; > + > &tmu_cpu0 { > vtmu-supply = <&ldo10_reg>; > }; > diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi > index 9c3b63b7cac6..02d34957cd83 100644 > --- a/arch/arm/boot/dts/exynos54xx.dtsi > +++ b/arch/arm/boot/dts/exynos54xx.dtsi > @@ -45,6 +45,15 @@ > status = "disabled"; > }; > > + timer: timer { > + compatible = "arm,armv7-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > + clock-frequency = <24000000>; > + }; > + > soc: soc { > sysram@2020000 { > compatible = "mmio-sram"; > diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts > index e0f470fe54c8..5e8cec736444 100644 > --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts > +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts > @@ -1033,6 +1033,10 @@ > status = "okay"; > }; > > +&timer { > + arm,cpu-registers-not-fw-configured; > +}; > + > &tmu_cpu0 { > vtmu-supply = <&ldo10_reg>; > }; > I tested it on odroid-xu3 to enable arch-timer for KVM. In result, I could just initialize KVM on xu3 without problem. Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
On Wed, Aug 28, 2019 at 02:10:04PM +0200, Marek Szyprowski wrote: > All CortexA7/A15 based Exynos5 SoCs have ARM architected timers, so enable > support for them directly in the base dtsi. None of the known firmware > properly configures CNTFRQ arch timer register, so force clock frequency > to 24MHz, which is the only configuration supported by the remaining > clock drivers so far. > > Stock firmware for Peach Pit and Pi Chromebooks also doesn't reset > properly other arch timer registers, so add respective properties > indicating that. Other Exynos5-based boards behaves correctly in this area, > what finally allows to enable support for KVM-based virtualization. > > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > --- > arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 ++++ > arch/arm/boot/dts/exynos54xx.dtsi | 9 +++++++++ > arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++++ Thanks, applied. Best regards, Krzysztof
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index f78db6809cca..77e08a4c7300 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -1064,6 +1064,10 @@ status = "okay"; }; +&timer { + arm,cpu-registers-not-fw-configured; +}; + &tmu_cpu0 { vtmu-supply = <&ldo10_reg>; }; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 9c3b63b7cac6..02d34957cd83 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -45,6 +45,15 @@ status = "disabled"; }; + timer: timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + }; + soc: soc { sysram@2020000 { compatible = "mmio-sram"; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index e0f470fe54c8..5e8cec736444 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -1033,6 +1033,10 @@ status = "okay"; }; +&timer { + arm,cpu-registers-not-fw-configured; +}; + &tmu_cpu0 { vtmu-supply = <&ldo10_reg>; };
All CortexA7/A15 based Exynos5 SoCs have ARM architected timers, so enable support for them directly in the base dtsi. None of the known firmware properly configures CNTFRQ arch timer register, so force clock frequency to 24MHz, which is the only configuration supported by the remaining clock drivers so far. Stock firmware for Peach Pit and Pi Chromebooks also doesn't reset properly other arch timer registers, so add respective properties indicating that. Other Exynos5-based boards behaves correctly in this area, what finally allows to enable support for KVM-based virtualization. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> --- arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 ++++ arch/arm/boot/dts/exynos54xx.dtsi | 9 +++++++++ arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++++ 3 files changed, 17 insertions(+)