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Tue, 11 Aug 2020 15:13:03 +0000 (GMT) From: Sylwester Nawrocki To: linux-clk@vger.kernel.org Cc: tomasz.figa@gmail.com, cw00.choi@samsung.com, sboyd@kernel.org, mturquette@baylibre.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, b.zolnierkie@samsung.com, m.szyprowski@samsung.com, Sylwester Nawrocki Subject: [PATCH v2 2/2] clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks Date: Tue, 11 Aug 2020 17:12:51 +0200 Message-Id: <20200811151251.31613-2-s.nawrocki@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200811151251.31613-1-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupileLIzCtJLcpLzFFi42LZduznOd2GrUbxBs+vyVhsnLGe1eL6l+es Fh977rFaXN41h81ixvl9TBZrj9xlt7h4ytXi8Jt2Vot/1zayWKza9YfRgcvj/Y1Wdo+ds+6y e2xa1cnm0bdlFaPH501yAaxRXDYpqTmZZalF+nYJXBld3UvYC24JVXyY/pOlgXE7fxcjJ4eE gInE8VsNjF2MXBxCAisYJdZNWscK4XxhlHj8ci4zhPOZUeJO+2VGmJZL9ycwQSSWM0r8X7qf Da7lzoP9rCBVbAKGEr1H+8A6RARkJW4d+wlWxCzQzCTxub+JpYuRg0NYIFniz29XkBoWAVWJ i0efM4PYvALWErs67rBDbJOXWL3hAFicU8BG4szfm2DHSgi0s0u8/X2dGaLIReLsjGWsELaw xKvjW6CaZSROT+5hgWhoZpTo2X2bHcKZwChx//gCqIesJe6c+8UGchGzgKbE+l36EGFHiUuT 37KChCUE+CRuvBUECTMDmZO2TWeGCPNKdLQJQVSrSPxeNZ0JwpaS6H7ynwWixEPi1zJPSPj0 M0rs6HvLPIFRfhbCrgWMjKsYxVNLi3PTU4uN8lLL9YoTc4tL89L1kvNzNzECU8jpf8e/7GDc 9SfpEKMAB6MSD++CiUbxQqyJZcWVuYcYJTiYlUR4nc6ejhPiTUmsrEotyo8vKs1JLT7EKM3B oiTOa7zoZayQQHpiSWp2ampBahFMlomDU6qBsVbx7lr/q792qPFej9Od0L3eau2LzXN2Gsh1 e/zfc2D7Co4Kq2OF/793mamHba6zzzyRXuz80cPXQfWSuyWHos2fJRHC/k4ii78Z1tbtl0s/ 4aZnuzu0dpZa8dmFVXu5Rdutt/x/KiQX7CTFqz3xTWHV+v5lzO6dKx7wlok7Mtb/fiZ55OwC JZbijERDLeai4kQA6mouPx0DAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNLMWRmVeSWpSXmKPExsVy+t/xu7r1W43iDbquW1lsnLGe1eL6l+es Fh977rFaXN41h81ixvl9TBZrj9xlt7h4ytXi8Jt2Vot/1zayWKza9YfRgcvj/Y1Wdo+ds+6y e2xa1cnm0bdlFaPH501yAaxRejZF+aUlqQoZ+cUltkrRhhZGeoaWFnpGJpZ6hsbmsVZGpkr6 djYpqTmZZalF+nYJehld3UvYC24JVXyY/pOlgXE7fxcjJ4eEgInEpfsTmLoYuTiEBJYySmw4 0sfaxcgBlJCSmN+iBFEjLPHnWhcbRM0nRomfG46zgiTYBAwleo/2MYLYIgKyEreO/QQrYhbo ZZJo/76FBSQhLJAocfdEB5jNIqAqcfHoc2YQm1fAWmJXxx12iA3yEqs3HACLcwrYSJz5exNs qBBQzczeU+wTGPkWMDKsYhRJLS3OTc8tNtQrTswtLs1L10vOz93ECAzobcd+bt7BeGlj8CFG AQ5GJR7eBRON4oVYE8uKK3MPMUpwMCuJ8DqdPR0nxJuSWFmVWpQfX1Sak1p8iNEU6KiJzFKi yfnAaMsriTc0NTS3sDQ0NzY3NrNQEuftEDgYIySQnliSmp2aWpBaBNPHxMEp1cA42YzL/ujj WbaBpq94dKcLsoUys29b4vH+zRK7Z3InLvzsuF4qOt1Y/47NZbO2lI6V9z4eLvnQK7T+MYd/ xtOX/4UORf6b5MR+imP6OUM+M/8MAc21yxdqe2s85qsTuXe+2I5TsnFKwC//nE1/Qx0kbX2q ugX2cr+7ecuU+9zZ6NoKx5Q3OcJKLMUZiYZazEXFiQBh8deXfgIAAA== X-CMS-MailID: 20200811151304eucas1p2c113097f89229b51bb55329c38990830 X-Msg-Generator: CA X-RootMTR: 20200811151304eucas1p2c113097f89229b51bb55329c38990830 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200811151304eucas1p2c113097f89229b51bb55329c38990830 References: <20200811151251.31613-1-s.nawrocki@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch adds a clk ID to the mout_sw_aclk_g3d clk definition so related clk pointer gets cached in the driver's private data and can be used later instead of a __clk_lookup() call. With that we have all clocks used in the clk_prepare_enable() calls in the clk provider init callback cached in clk_data.hws[] and we can reference the clk pointers directly rather than using __clk_lookup() with global names. Signed-off-by: Sylwester Nawrocki Reported-by: Marek Szyprowski Signed-off-by: Sylwester Nawrocki --- Changes for v2: - added missing part of the patch lost during rebase of the previous version --- drivers/clk/samsung/clk-exynos5420.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index bd62087..f76ebd6 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -712,8 +712,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { SRC_TOP12, 8, 1), MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, SRC_TOP12, 12, 1), - MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1, - CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, + SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0), MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", @@ -1560,6 +1560,7 @@ static void __init exynos5x_clk_init(struct device_node *np, enum exynos5x_soc soc) { struct samsung_clk_provider *ctx; + struct clk_hw **hws; if (np) { reg_base = of_iomap(np, 0); @@ -1649,17 +1650,18 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_subcmus); } + hws = ctx->clk_data.hws; /* * Keep top part of G3D clock path enabled permanently to ensure * that the internal busses get their clock regardless of the * main G3D clock enablement status. */ - clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d")); + clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk); /* * Keep top BPLL mux enabled permanently to ensure that DRAM operates * properly. */ - clk_prepare_enable(__clk_lookup("mout_bpll")); + clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk); samsung_clk_of_add_provider(np, ctx); }