| Message ID | 20201202122029.22198-1-m.szyprowski@samsung.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 7995fb896b9637a5f59a56ae0d8f2b7ca71a040d |
| Headers | show |
| Series | ARM: dts: exynos: Reduce assigned-clocks entries for SPI0 on Artik5 board | expand |
On Wed, 2 Dec 2020 13:20:29 +0100, Marek Szyprowski wrote: > Commit 2024b130b0c8 ("ARM: dts: exynos: Add Ethernet to Artik 5 board") > added ethernet chip on SPI0 bus and the whole bunch of assigned clock > entries to ensure proper clock rates and topology. Limit the assigned > clock parents only to the direct clocks of the SPI0 device and assume > that MPLL clock is already properly configured. > > The applied clock topology was incorrect as some clocks between were > missing, what resulted in the following warning: > > [...] Applied, thanks! [1/1] ARM: dts: exynos: Reduce assigned-clocks entries for SPI0 on Artik5 board commit: 7995fb896b9637a5f59a56ae0d8f2b7ca71a040d Best regards,
diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts index 5461949d833e..a1e22f630638 100644 --- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts +++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts @@ -42,12 +42,9 @@ status = "okay"; cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>; - assigned-clocks = <&cmu CLK_MOUT_MPLL>, <&cmu CLK_DIV_MPLL_PRE>, - <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, + assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>; - assigned-clock-parents = <&cmu CLK_FOUT_MPLL>, /* for: CLK_MOUT_MPLL */ - <&cmu CLK_MOUT_MPLL>, /* for: CLK_DIV_MPLL_PRE */ - <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ + assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */ <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */ <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */
Commit 2024b130b0c8 ("ARM: dts: exynos: Add Ethernet to Artik 5 board") added ethernet chip on SPI0 bus and the whole bunch of assigned clock entries to ensure proper clock rates and topology. Limit the assigned clock parents only to the direct clocks of the SPI0 device and assume that MPLL clock is already properly configured. The applied clock topology was incorrect as some clocks between were missing, what resulted in the following warning: clk: failed to reparent div_mpll_pre to mout_mpll: -22 Fixes: 2024b130b0c8 ("ARM: dts: exynos: Add Ethernet to Artik 5 board") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> --- arch/arm/boot/dts/exynos3250-artik5-eval.dts | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-)