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Wed, 2 Dec 2020 12:20:35 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Krzysztof Kozlowski , Lukasz Stelmach , Bartlomiej Zolnierkiewicz , Chanwoo Choi Subject: [PATCH] ARM: dts: exynos: Reduce assigned-clocks entries for SPI0 on Artik5 board Date: Wed, 2 Dec 2020 13:20:29 +0100 Message-Id: <20201202122029.22198-1-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKIsWRmVeSWpSXmKPExsWy7djP87pT2o7HG3yeyWOxccZ6VovrX56z Wpw/v4Hd4uahFYwWM87vY7JYe+QuuwObx6ZVnWwefVtWMXp83iQXwBzFZZOSmpNZllqkb5fA lTH3yj+Wgm6+il3vPzI3MF7j7mLk5JAQMJHYMXcHYxcjF4eQwApGiUe9z9ghnC+MErcO9TFB OJ8ZJToaJ7LAtOxffhoqsZxR4uT3DaxwLZu6NoJVsQkYSnS97WIDsUUEVCU+ty0Am8ss8IhR 4u3EVewgCWGBGIk9kyaB2SxARce3bwRr4BWwlWh99YwJYp28xOoNB5hBmiUE3rJLHG04zAyR cJH4dfwTlC0s8er4FnYIW0bi/875TBANzYwSD8+tZYdwehglLjfNYISospa4c+4X0DoOoJs0 Jdbv0ocIO0pMWLmNBSQsIcAnceOtIEiYGcictG06M0SYV6KjTQiiWk1i1vF1cGsPXrgEdY6H xPmfV8F+ERKIlZj66TXbBEa5WQi7FjAyrmIUTy0tzk1PLTbMSy3XK07MLS7NS9dLzs/dxAiM +dP/jn/awTj31Ue9Q4xMHIyHGCU4mJVEeFn+HYkX4k1JrKxKLcqPLyrNSS0+xCjNwaIkzrtq 9pp4IYH0xJLU7NTUgtQimCwTB6dUA1PMjcsa+xV3sK7XZOvjyWtpOLpFICXhwKElOenX0q7V 5ly8E9ifW7m3sm/q8k3qtuwL+VZv7pD9YzBHOy+qrL/F7uV/jdrQuZPn2vi0fT667bizi35h 6b6oygtq73tUuf9KZ85dYmrD9my+Vcg7Tc5Dk3f8P5BSd1SXZUdXxtT9By6ltKlYnnjRuGDX poAbL91Vd09+eqz15t7/c2e3Nv6IO/p7S7zKo3P8jYfMco7IryyvDmf02r5lncnuHI2yBY0m mSumdNW8/XBJ8Iv/udN/2TZeECye81mXb35jnUbEJOVnm6WvPv2z/UZADtu3AyJHvc5mJmmv P6DXajp7w/XMrHORXGJhLDx1b8w+PdmlxFKckWioxVxUnAgA/2aInmgDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrFLMWRmVeSWpSXmKPExsVy+t/xe7qT247HG0zsULfYOGM9q8X1L89Z Lc6f38BucfPQCkaLGef3MVmsPXKX3YHNY9OqTjaPvi2rGD0+b5ILYI7SsynKLy1JVcjILy6x VYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQy5h75R9LQTdfxa73H5kbGK9x dzFyckgImEjsX36aqYuRi0NIYCmjxJXjL1ghEjISJ6c1QNnCEn+udbFBFH1ilJjzpocNJMEm YCjR9bYLzBYRUJX43LaAHaSIWeAJo8Tt3kXMIAlhgSiJPVtusYDYLEBFx7dvBGvgFbCVaH31 jAlig7zE6g0HmCcw8ixgZFjFKJJaWpybnltspFecmFtcmpeul5yfu4kRGGjbjv3csoNx5auP eocYmTgYDzFKcDArifCy/DsSL8SbklhZlVqUH19UmpNafIjRFGjfRGYp0eR8YKjnlcQbmhmY GpqYWRqYWpoZK4nzmhxZEy8kkJ5YkpqdmlqQWgTTx8TBKdXAxHrzodO7kHtVE0wi9/MGvf6v 5+g45V6UalLWp1dTd3KGudasY8lTv80oefCz8duNGj9mnn4pcvXndpHMT76f9Bbn1iZ89mTS NJtzoW5v47KIQywPVVdf+vp0oV3t5uzty0yDS3a/y/+wiCFU3mjd8eMXa3xfGHTJ/Cw5Fhbf 32xyofh8bZTmSRHnG6s7T/99L7VcbVqPvsypt7eNp7SELfvZ8uvRh8x5Ks+u1u/kUV2zPOX4 GXbtZZubI7atTZrx5d5v8QU3/OY1s/+euyB5o8lrebaE1xf3rH69/k+ViI5pSM69Pwc5G18r 72mrfHzZ7XAmg1dc8swUWcPVldcrD8yOz2Wwu/7+6ZWXXlL1cS+VWIozEg21mIuKEwGzROgq vQIAAA== X-CMS-MailID: 20201202122035eucas1p175944617fd50292f7dccc775823ed038 X-Msg-Generator: CA X-RootMTR: 20201202122035eucas1p175944617fd50292f7dccc775823ed038 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201202122035eucas1p175944617fd50292f7dccc775823ed038 References: Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Commit 2024b130b0c8 ("ARM: dts: exynos: Add Ethernet to Artik 5 board") added ethernet chip on SPI0 bus and the whole bunch of assigned clock entries to ensure proper clock rates and topology. Limit the assigned clock parents only to the direct clocks of the SPI0 device and assume that MPLL clock is already properly configured. The applied clock topology was incorrect as some clocks between were missing, what resulted in the following warning: clk: failed to reparent div_mpll_pre to mout_mpll: -22 Fixes: 2024b130b0c8 ("ARM: dts: exynos: Add Ethernet to Artik 5 board") Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos3250-artik5-eval.dts | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts index 5461949d833e..a1e22f630638 100644 --- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts +++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts @@ -42,12 +42,9 @@ status = "okay"; cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>; - assigned-clocks = <&cmu CLK_MOUT_MPLL>, <&cmu CLK_DIV_MPLL_PRE>, - <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, + assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>; - assigned-clock-parents = <&cmu CLK_FOUT_MPLL>, /* for: CLK_MOUT_MPLL */ - <&cmu CLK_MOUT_MPLL>, /* for: CLK_DIV_MPLL_PRE */ - <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ + assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */ <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */ <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */