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Tue, 22 Jun 2021 13:02:03 +0000 (GMT) From: Alim Akhtar To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org Cc: krzysztof.kozlowski@canonical.com, linux-samsung-soc@vger.kernel.org, Alim Akhtar Subject: [PATCH v2 2/2] arm64: dts: exynos5433: Add cpu cache information Date: Tue, 22 Jun 2021 18:35:51 +0530 Message-Id: <20210622130551.67446-2-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210622130551.67446-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrHIsWRmVeSWpSXmKPExsWy7bCmhq78g4sJBk2NkhYP5m1js9j49geT xabH11gtLu+aw2Yx4/w+JovWvUfYHdg8ZjX0snlsWtXJ5rF5Sb1H35ZVjB6fN8kFsEZx2aSk 5mSWpRbp2yVwZdxq2MJa0K9QcXF6P1MD40uJLkZODgkBE4mrd36xdDFycQgJ7GaUWPbnCDuE 84lRYuqcuVCZb4wSK+c+ZYVp2bOilxkisZdR4vWm1YwQTguTxNru7+wgVWwC2hJ3p29hArFF BGIkHu6ZB9bNLFAo8aLlJliNsICnRFPvO0YQm0VAVeL1rbMsIDavgI3E1HN7WCC2yUus3nCA GcTmFLCVmDTlEth9EgL72CVOfzjIDlHkIvFu/xEoW1ji1fEtULaUxOd3e9m6GDmA7GyJnl3G EOEaiaXzjkHNt5c4cGUOC0gJs4CmxPpd+hBhWYmpp9YxQZzMJ9H7+wkTRJxXYsc8GFtVovnd Vagx0hITu7tZITZ5SLT0pECCZAKjxPRPM5gnMMrNQtiwgJFxFaNkakFxbnpqsWmBYV5quV5x Ym5xaV66XnJ+7iZGcBLQ8tzBePfBB71DjEwcjIcYJTiYlUR4X2RfTBDiTUmsrEotyo8vKs1J LT7EKM3BoiTOu5T9UIKQQHpiSWp2ampBahFMlomDU6qBaf4uny1eiWmMLltN1+i/jeC9eclY 4O6xmaL/ZF7YHGlsZnR3lftpP9H7oVA964/pu0/mPrk18Z74rRePru89aZLkp3CxiOfUKf8V 6ufnWresydruvX3hyuXF+5ft3rjAYavpeuG47tClztoa5tVPP7w5H7zP98OLGexr2CUfzZgq 33VaSfhOUdnreQdWLsy5vXv3bb7ynVIv3j802/PtyOquVykNJyfvW8X2QVYy+1BlId+Zlyad Ah+Tk9p+XFCIyZ7+0Cx3QvZVpUnaK9MKHNNKztkrn5wqx3nk0hv2Q7FnZ+nutjjA+6H77tl5 hzQbKvhljLfH77t8e/8f96tdZwx3neiv1dl6c0Eob77kvLarSizFGYmGWsxFxYkAxQGma3ED AAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjluLIzCtJLcpLzFFi42LZdlhJTtfn/sUEg3nXVCwezNvGZrHx7Q8m i02Pr7FaXN41h81ixvl9TBate4+wO7B5zGroZfPYtKqTzWPzknqPvi2rGD0+b5ILYI3isklJ zcksSy3St0vgyrjVsIW1oF+h4uL0fqYGxpcSXYycHBICJhJ7VvQydzFycQgJ7GaU2HXiFwtE Qlri+sYJ7BC2sMTKf8/BbCGBJiaJv501IDabgLbE3elbmLoYOThEBOIkWtdXg5jMAsUSp38x gVQIC3hKNPW+YwSxWQRUJV7fOgs2nVfARmLquT1Qm+QlVm84wAxicwrYSkyacglqk43E4rWr mCcw8i1gZFjFKJlaUJybnltsWGCYl1quV5yYW1yal66XnJ+7iREcZFqaOxi3r/qgd4iRiYPx EKMEB7OSCO+L7IsJQrwpiZVVqUX58UWlOanFhxilOViUxHkvdJ2MFxJITyxJzU5NLUgtgsky cXBKNTCt49coLdsYZfvzmYZAZCIfzz7ByqPms2541n4KYLu/0+dWyW+28ocVP66zvrq+3uKi hc+MZXPu/b32dsF3IRNfoW5Om2tb+N5bZS+46zavqHGDlkbOlcdHfu4zK/fttf4h+PbOPxfV 7prNL62XSN8R6FrSV6P59870uI9zdh/x7eDavfR4xEz1VSUvo7Uq93NNszyrlOV8TedHusXL rYI72L1M1Nbde6Cp5DJ/RbjFg9QyicRY1ZgqM/5NKZKcke0bxC5/+S7z9XD195mTA7fsDPju 0C15L/o2243ju3o/XGUT3MWv5CKdkXk64/daqe2ptlXzeCbmPH5ZfeBLhrGStuLxmgNL0zW/ TQmvq0lSYinOSDTUYi4qTgQAUlcJN6ECAAA= X-CMS-MailID: 20210622130204epcas5p1192cd38abc4a0b49798355cecea9f763 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20210622130204epcas5p1192cd38abc4a0b49798355cecea9f763 References: <20210622130551.67446-1-alim.akhtar@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch adds cpu caches information to its dt nodes so that the same is available to userspace via sysfs. This SoC has 48/32 KB I/D cache for each A57 cores with 2MB L2 cache. And 32/32 KB I/D cache for each A53 cores with 256KB L2 cache. Signed-off-by: Alim Akhtar --- -Changes since v1: * addressed Krzysztof's review comments arch/arm64/boot/dts/exynos/exynos5433.dtsi | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 18a912eee360..73aa0fa9b778 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -62,6 +62,13 @@ clock-names = "apolloclk"; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&cluster_a53_l2>; }; cpu1: cpu@101 { @@ -72,6 +79,13 @@ clock-frequency = <1300000000>; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&cluster_a53_l2>; }; cpu2: cpu@102 { @@ -82,6 +96,13 @@ clock-frequency = <1300000000>; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&cluster_a53_l2>; }; cpu3: cpu@103 { @@ -92,6 +113,13 @@ clock-frequency = <1300000000>; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&cluster_a53_l2>; }; cpu4: cpu@0 { @@ -104,6 +132,13 @@ clock-names = "atlasclk"; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cluster_a57_l2>; }; cpu5: cpu@1 { @@ -114,6 +149,13 @@ clock-frequency = <1900000000>; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cluster_a57_l2>; }; cpu6: cpu@2 { @@ -124,6 +166,13 @@ clock-frequency = <1900000000>; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cluster_a57_l2>; }; cpu7: cpu@3 { @@ -134,6 +183,27 @@ clock-frequency = <1900000000>; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cluster_a57_l2>; + }; + + cluster_a57_l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; + }; + + cluster_a53_l2: l2-cache1 { + compatible = "cache"; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <256>; }; };