| Message ID | 20210917065436.145629-6-chanho61.park@samsung.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | introduce exynosauto v9 ufs driver | expand |
On Fri, Sep 17, 2021 at 03:54:24PM +0900, Chanho Park wrote: > Add "sysreg" regmap phandle property to control io coherency setting. > > Cc: Rob Herring <robh+dt@kernel.org> > Cc: devicetree@vger.kernel.org > Signed-off-by: Chanho Park <chanho61.park@samsung.com> > --- > .../devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml > index b9ca8ef4f2be..c3f14f81d4b7 100644 > --- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml > +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml > @@ -54,6 +54,11 @@ properties: > phy-names: > const: ufs-phy > > + sysreg: Needs a vendor prefix. > + $ref: '/schemas/types.yaml#/definitions/phandle' > + description: phandle for FSYS sysreg interface, used to control > + sysreg register bit for UFS IO Coherency Is there more than 1 FSYS? If not, you can just get the node by its compatible. Also, what about 'dma-coherent' property? The driver core needs to know. > + > required: > - compatible > - reg > -- > 2.33.0 > >
> > + sysreg: > > Needs a vendor prefix. Thanks. I'll use "samsung,sysreg-phandle". > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > + description: phandle for FSYS sysreg interface, used to control > > + sysreg register bit for UFS IO Coherency > > Is there more than 1 FSYS? If not, you can just get the node by its > compatible. The phandle can be differed each exynos SoCs, AFAIK. I think other exynos SoCs since exnos7 will need this but not upstreamed yet... > > Also, what about 'dma-coherent' property? The driver core needs to know. Yes. 'dma-coherent' should be listed as well. Best Regards, Chanho Park
On Thu, Sep 23, 2021 at 09:47:44AM +0900, Chanho Park wrote: > > > + sysreg: > > > > Needs a vendor prefix. > > Thanks. I'll use "samsung,sysreg-phandle". No '-phandle'. > > > > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > + description: phandle for FSYS sysreg interface, used to control > > > + sysreg register bit for UFS IO Coherency > > > > Is there more than 1 FSYS? If not, you can just get the node by its > > compatible. > > The phandle can be differed each exynos SoCs, AFAIK. I think other exynos > SoCs since exnos7 will need this but not upstreamed yet... That's still fine. You really only need a phandle if there is more than 1 instance on a given platform. Of course you could end up with multiple compatible strings to deal with, but you might need that anyway as the registers are likely to be different. That can sometimes be mitigated by putting register offsets into the DT property (something to consider here). This is the problem with drivers directly twiddling bits in other h/w blocks and why we have common interfaces for clocks, resets, etc. I leave it to you to decide how you want to do it. BTW, If you want to see another way to handle the same problem, see highbank_platform_notifier(). Notifiers aren't great either, but it keeps some SoC specifics out of the driver. Rob
> > > > + sysreg: > > > > > > Needs a vendor prefix. > > > > Thanks. I'll use "samsung,sysreg-phandle". > > No '-phandle'. Will use "samsung,sysreg" next patch series. > > > > > > > > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > > + description: phandle for FSYS sysreg interface, used to control > > > > + sysreg register bit for UFS IO Coherency > > > > > > Is there more than 1 FSYS? If not, you can just get the node by its > > > compatible. > > > > The phandle can be differed each exynos SoCs, AFAIK. I think other > > exynos SoCs since exnos7 will need this but not upstreamed yet... > > That's still fine. You really only need a phandle if there is more than > 1 instance on a given platform. > > Of course you could end up with multiple compatible strings to deal with, > but you might need that anyway as the registers are likely to be different. > That can sometimes be mitigated by putting register offsets into the DT > property (something to consider here). This is the problem with drivers > directly twiddling bits in other h/w blocks and why we have common > interfaces for clocks, resets, etc. Regarding ufs-exynos, it can have multiple instances (ufs_0/1/22). I'm also preparing to support ufs_1 for exynosautov9 SoC but not yet finished due to ufs phy control. Each instances has their own sysreg offset. To support secondary ufs, I need to rework this patch and add the offset field as DT propery. +#define UFS_SHAREABILITY_OFFSET 0x710 For UFS1, this should be 0x714. > > I leave it to you to decide how you want to do it. > > BTW, If you want to see another way to handle the same problem, see > highbank_platform_notifier(). Notifiers aren't great either, but it keeps > some SoC specifics out of the driver. > I checked highbank_platform_notifier() implementation but I need to keep this way to have further support multiple ufs instances and can be used for exynos8/9 SoCs as well. Best Regards, Chanho Park
diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml index b9ca8ef4f2be..c3f14f81d4b7 100644 --- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml @@ -54,6 +54,11 @@ properties: phy-names: const: ufs-phy + sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for FSYS sysreg interface, used to control + sysreg register bit for UFS IO Coherency + required: - compatible - reg
Add "sysreg" regmap phandle property to control io coherency setting. Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Chanho Park <chanho61.park@samsung.com> --- .../devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 5 +++++ 1 file changed, 5 insertions(+)