| Message ID | 20211112010137.149174-2-jaewon02.kim@samsung.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | i2c: exynos5: add support for ExynosAutov9 SoC | expand |
On Fri, 12 Nov 2021 at 03:06, Jaewon Kim <jaewon02.kim@samsung.com> wrote: > > This patch adds new "samsung,exynosautov9-hsi2c" compatible. > It is for i2c compatible with HSI2C available on Exynos SoC with USI. > > Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > --- Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Documentation/devicetree/bindings/i2c/i2c-exynos5.txt | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt > index 2dbc0b62daa6..39f4067d9d1f 100644 > --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt > +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt > @@ -14,6 +14,8 @@ Required properties: > on Exynos5260 SoCs. > -> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available > on Exynos7 SoCs. > + -> "samsung,exynosautov9-hsi2c", for i2c compatible with HSI2C available > + on ExynosAutov9 SoCs. > > - reg: physical base address of the controller and length of memory mapped > region. > @@ -31,6 +33,11 @@ Optional properties: > at 100khz. > -> If specified, the bus operates in high-speed mode only if the > clock-frequency is >= 1Mhz. > + - samsung,sysreg : system registers controller phandle to control USI. > + -> If I2C integrated to USI(Universal Serial Interface), this property > + is required. When using Exynos USI block, it needs to select which type > + of Serial IPs(UART, SPI, I2C) to use with system register. So, it > + requires samsung,sysreg phandle and offset value of system register. > > Example: > > -- > 2.33.1 >
On 12/11/2021 02:01, Jaewon Kim wrote: > This patch adds new "samsung,exynosautov9-hsi2c" compatible. > It is for i2c compatible with HSI2C available on Exynos SoC with USI. > > Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Thanks Jaewon for your patch. After more discussions and remarks from David, I think we should go with dedicated USI driver instead of using sysreg/syscon in every I2C/UART/SPI. Therefore I want to remove my reviewed-by and instead ask to work on dedicated USI driver (option 1 from Chanho's email). It's not that this solution is anything bad, just it won't be flexible to support USIv1. It will also lead to duplicated - and possibly conflicting - USI configuration in each of drivers (I2C/UART/SPI). > --- > Documentation/devicetree/bindings/i2c/i2c-exynos5.txt | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt > index 2dbc0b62daa6..39f4067d9d1f 100644 > --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt > +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt > @@ -14,6 +14,8 @@ Required properties: > on Exynos5260 SoCs. > -> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available > on Exynos7 SoCs. > + -> "samsung,exynosautov9-hsi2c", for i2c compatible with HSI2C available > + on ExynosAutov9 SoCs. > > - reg: physical base address of the controller and length of memory mapped > region. > @@ -31,6 +33,11 @@ Optional properties: > at 100khz. > -> If specified, the bus operates in high-speed mode only if the > clock-frequency is >= 1Mhz. > + - samsung,sysreg : system registers controller phandle to control USI. > + -> If I2C integrated to USI(Universal Serial Interface), this property > + is required. When using Exynos USI block, it needs to select which type > + of Serial IPs(UART, SPI, I2C) to use with system register. So, it > + requires samsung,sysreg phandle and offset value of system register. > > Example: > > Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt index 2dbc0b62daa6..39f4067d9d1f 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt @@ -14,6 +14,8 @@ Required properties: on Exynos5260 SoCs. -> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available on Exynos7 SoCs. + -> "samsung,exynosautov9-hsi2c", for i2c compatible with HSI2C available + on ExynosAutov9 SoCs. - reg: physical base address of the controller and length of memory mapped region. @@ -31,6 +33,11 @@ Optional properties: at 100khz. -> If specified, the bus operates in high-speed mode only if the clock-frequency is >= 1Mhz. + - samsung,sysreg : system registers controller phandle to control USI. + -> If I2C integrated to USI(Universal Serial Interface), this property + is required. When using Exynos USI block, it needs to select which type + of Serial IPs(UART, SPI, I2C) to use with system register. So, it + requires samsung,sysreg phandle and offset value of system register. Example: