diff mbox series

arm64: dts: fsd: Add the MCT support

Message ID 20220223171858.11384-1-alim.akhtar@samsung.com (mailing list archive)
State Accepted
Commit 272a253338f91a192defc124930030369b2a7fd4
Headers show
Series arm64: dts: fsd: Add the MCT support | expand

Commit Message

Alim Akhtar Feb. 23, 2022, 5:18 p.m. UTC 
Add node relevant to support MCT, which is used as
one of the system timer on this SoC.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 arch/arm64/boot/dts/tesla/fsd.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

Comments

Krzysztof Kozlowski Feb. 24, 2022, 11:31 a.m. UTC | #1 
On Wed, 23 Feb 2022 22:48:58 +0530, Alim Akhtar wrote:
> Add node relevant to support MCT, which is used as
> one of the system timer on this SoC.
> 
> 

Applied, thanks!

[1/1] arm64: dts: fsd: Add the MCT support
      commit: 272a253338f91a192defc124930030369b2a7fd4

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index da4acd68b976..9a652abcbcac 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -725,6 +725,29 @@  spi_2: spi@14160000 {
 			num-cs = <1>;
 			status = "disabled";
 		};
+
+		timer@10040000 {
+			compatible = "samsung,exynos4210-mct";
+			reg = <0x0 0x10040000 0x0 0x800>;
+			interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
+			clock-names = "fin_pll", "mct";
+		};
 	};
 };