| Message ID | 20220225153650.289923-2-krzysztof.kozlowski@canonical.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | cca50a59f60a6b2b5aa2c90d8c173da89f567ee3 |
| Headers | show |
| Series | [1/3] dt-bindings: timer: exynos4210-mct: describe known hardware and its interrupts | expand |
>-----Original Message----- >From: Krzysztof Kozlowski [mailto:krzysztof.kozlowski@canonical.com] >Sent: Friday, February 25, 2022 9:07 PM >To: Daniel Lezcano <daniel.lezcano@linaro.org>; Thomas Gleixner ><tglx@linutronix.de>; Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski ><krzysztof.kozlowski@canonical.com>; Alim Akhtar ><alim.akhtar@samsung.com>; linux-kernel@vger.kernel.org; >devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- >samsung-soc@vger.kernel.org >Subject: [PATCH 2/3] ARM: dts: exynos: add a specific compatible to MCT > >One compatible is used for the Multi-Core Timer on most of the Samsung Exynos >SoCs, which is correct but not specific enough. These MCT blocks have different >number of interrupts, so add a second specific compatible to Exynos3250 and all >Exynos5 SoCs. > >Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> >--- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> > arch/arm/boot/dts/exynos3250.dtsi | 3 ++- arch/arm/boot/dts/exynos5250.dtsi >| 3 ++- arch/arm/boot/dts/exynos5260.dtsi | 3 ++- >arch/arm/boot/dts/exynos54xx.dtsi | 3 ++- > 4 files changed, 8 insertions(+), 4 deletions(-) > >diff --git a/arch/arm/boot/dts/exynos3250.dtsi >b/arch/arm/boot/dts/exynos3250.dtsi >index ae644315855d..41bb421e67c2 100644 >--- a/arch/arm/boot/dts/exynos3250.dtsi >+++ b/arch/arm/boot/dts/exynos3250.dtsi >@@ -269,7 +269,8 @@ gic: interrupt-controller@10481000 { > }; > > timer@10050000 { >- compatible = "samsung,exynos4210-mct"; >+ compatible = "samsung,exynos3250-mct", >+ "samsung,exynos4210-mct"; > reg = <0x10050000 0x800>; > interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, diff -- >git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi >index 5baaa7eb71a4..63d1dcf2c55c 100644 >--- a/arch/arm/boot/dts/exynos5250.dtsi >+++ b/arch/arm/boot/dts/exynos5250.dtsi >@@ -245,7 +245,8 @@ clock_audss: audss-clock-controller@3810000 { > }; > > timer@101c0000 { >- compatible = "samsung,exynos4210-mct"; >+ compatible = "samsung,exynos5250-mct", >+ "samsung,exynos4210-mct"; > reg = <0x101C0000 0x800>; > clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; > clock-names = "fin_pll", "mct"; >diff --git a/arch/arm/boot/dts/exynos5260.dtsi >b/arch/arm/boot/dts/exynos5260.dtsi >index 56271e7c4587..ff1ee409eff3 100644 >--- a/arch/arm/boot/dts/exynos5260.dtsi >+++ b/arch/arm/boot/dts/exynos5260.dtsi >@@ -333,7 +333,8 @@ chipid: chipid@10000000 { > }; > > mct: timer@100b0000 { >- compatible = "samsung,exynos4210-mct"; >+ compatible = "samsung,exynos5260-mct", >+ "samsung,exynos4210-mct"; > reg = <0x100B0000 0x1000>; > clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; > clock-names = "fin_pll", "mct"; >diff --git a/arch/arm/boot/dts/exynos54xx.dtsi >b/arch/arm/boot/dts/exynos54xx.dtsi >index 2ddb7a5f12b3..3ec43761d8b9 100644 >--- a/arch/arm/boot/dts/exynos54xx.dtsi >+++ b/arch/arm/boot/dts/exynos54xx.dtsi >@@ -74,7 +74,8 @@ smp-sram@53000 { > }; > > mct: timer@101c0000 { >- compatible = "samsung,exynos4210-mct"; >+ compatible = "samsung,exynos5420-mct", >+ "samsung,exynos4210-mct"; > reg = <0x101c0000 0xb00>; > interrupts-extended = <&combiner 23 3>, > <&combiner 23 4>, >-- >2.32.0
On Fri, 25 Feb 2022 16:36:49 +0100, Krzysztof Kozlowski wrote: > One compatible is used for the Multi-Core Timer on most of the Samsung > Exynos SoCs, which is correct but not specific enough. These MCT blocks > have different number of interrupts, so add a second specific > compatible to Exynos3250 and all Exynos5 SoCs. > > Applied, thanks! [2/3] ARM: dts: exynos: add a specific compatible to MCT commit: cca50a59f60a6b2b5aa2c90d8c173da89f567ee3 Best regards,
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index ae644315855d..41bb421e67c2 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -269,7 +269,8 @@ gic: interrupt-controller@10481000 { }; timer@10050000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos3250-mct", + "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 5baaa7eb71a4..63d1dcf2c55c 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -245,7 +245,8 @@ clock_audss: audss-clock-controller@3810000 { }; timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5250-mct", + "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 56271e7c4587..ff1ee409eff3 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -333,7 +333,8 @@ chipid: chipid@10000000 { }; mct: timer@100b0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5260-mct", + "samsung,exynos4210-mct"; reg = <0x100B0000 0x1000>; clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; clock-names = "fin_pll", "mct"; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 2ddb7a5f12b3..3ec43761d8b9 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -74,7 +74,8 @@ smp-sram@53000 { }; mct: timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5420-mct", + "samsung,exynos4210-mct"; reg = <0x101c0000 0xb00>; interrupts-extended = <&combiner 23 3>, <&combiner 23 4>,
One compatible is used for the Multi-Core Timer on most of the Samsung Exynos SoCs, which is correct but not specific enough. These MCT blocks have different number of interrupts, so add a second specific compatible to Exynos3250 and all Exynos5 SoCs. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> --- arch/arm/boot/dts/exynos3250.dtsi | 3 ++- arch/arm/boot/dts/exynos5250.dtsi | 3 ++- arch/arm/boot/dts/exynos5260.dtsi | 3 ++- arch/arm/boot/dts/exynos54xx.dtsi | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-)