Message ID | 20220304122424.307885-4-krzysztof.kozlowski@canonical.com (mailing list archive) |
---|---|
State | Accepted |
Commit | 2616922241706ec5c2c5ae95d5ac1d3120575ded |
Headers | show |
Series | dt-bindings: timer: exynos4210-mct: describe known hardware and its interrupts | expand |
On Fri, 4 Mar 2022 13:24:23 +0100, Krzysztof Kozlowski wrote: > One compatible is used for the Multi-Core Timer on most of the Samsung > Exynos SoCs, which is correct but not specific enough. These MCT blocks > have different number of interrupts, so add a second specific > compatible to Exynos5433 and Exynos850. > > Applied, thanks! [3/4] arm64: dts: exynos: add a specific compatible to MCT commit: 2616922241706ec5c2c5ae95d5ac1d3120575ded Best regards,
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 661567d2dd7a..017ccc2f4650 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -806,7 +806,8 @@ tmu_isp: tmu@1007c000 { }; timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5433-mct", + "samsung,exynos4210-mct"; reg = <0x101c0000 0x800>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index d1700e96fee2..12f7ddc6fd0a 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -181,7 +181,8 @@ chipid@10000000 { }; timer@10040000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos850-mct", + "samsung,exynos4210-mct"; reg = <0x10040000 0x800>; interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,