| Message ID | 20220308142410.3193729-3-vincent.whitchurch@axis.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | clocksource: Add MCT support for ARTPEC-8 | expand |
On 08/03/2022 15:24, Vincent Whitchurch wrote: > The ARTPEC-8 SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 > which share one MCT with one global and eight local timers. The > Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and > therefore run two separate kernels. > > The Cortex-A53 boots first and starts the global FRC and also registers > a clock events device using the global timer. (This global timer clock > events is usually replaced by arch timer clock events for each of the > cores.) > > When the A5 boots, we should not use the global timer interrupts or > write to the global timer registers. This is because even if there are > four global comparators, the control bits for all four are in the same > registers, and we would need to synchronize between the cpus. Instead, > the global timer FRC (already started by the A53) should be used as the > clock source, and one of the local timers which are not used by the A53 > can be used for clock events on the A5. > > To support this usecase, add a property to the binding to specify the > first local timer index to be used. If this parameter is non-zero, the > global timer interrupts will also not be used. > > Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> > --- > > Notes: > v2: New. > > .../bindings/timer/samsung,exynos4210-mct.yaml | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml > index dce42f1f7574..46f466081836 100644 > --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml > +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml > @@ -47,6 +47,15 @@ properties: > reg: > maxItems: 1 > > + local-timer-index: You need vendor prefix. Also this should describe the actual hardware, not driver behavior, so rather: "samsung,local-timers" with a uint32-array type and list of timers to use. You also need separate property to skip FRC, so something like: "samsung,frc-shared" of type boolean. In the bindings please describe the hardware, not the result you want to achieve from driver model point of view. Also disallow this for all other compatibles: allOf: - if: not: properties: ... then: properties: samsung,local-timers: false samsung,frc-shared: false The property simply should not be used outside of Artpec8. It's not valid in other configurations. > + $ref: /schemas/types.yaml#/definitions/uint32 > + default: 0 > + maximum: 15 # Last local timer index > + description: | > + If present, sets the first local timer index to use. If this value is > + set to a non-default value, the global timer will not be used for > + interrupts. Do not describe the driver, but the hardware. Instead explain which local timers are allowed to be used. > + > interrupts: > description: | > Interrupts should be put in specific order. This is, the local timer Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index dce42f1f7574..46f466081836 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -47,6 +47,15 @@ properties: reg: maxItems: 1 + local-timer-index: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + maximum: 15 # Last local timer index + description: | + If present, sets the first local timer index to use. If this value is + set to a non-default value, the global timer will not be used for + interrupts. + interrupts: description: | Interrupts should be put in specific order. This is, the local timer
The ARTPEC-8 SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and therefore run two separate kernels. The Cortex-A53 boots first and starts the global FRC and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots, we should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this usecase, add a property to the binding to specify the first local timer index to be used. If this parameter is non-zero, the global timer interrupts will also not be used. Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> --- Notes: v2: New. .../bindings/timer/samsung,exynos4210-mct.yaml | 9 +++++++++ 1 file changed, 9 insertions(+)