| Message ID | 20220311094515.3223023-3-vincent.whitchurch@axis.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 1db536f95d0264a2b83fb032d5b057ba0113e622 |
| Headers | show |
| Series | Add support for ARTPEC-8 UART | expand |
On 11/03/2022 10:45, Vincent Whitchurch wrote: > Add support for the UART block on the ARTPEC-8 SoC. This is closely > related to the variants used on the Exynos chips. The register layout > is identical to Exynos850 et al but the fifo size is different (64 bytes > in each direction for all instances). > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> > --- > > Notes: > v2: > - Added Krzysztof's Reviewed-by. > - Expanded commit message > - Fixed fifo size > - Rebased on top of Krzysztof's "minor fixes/cleanups" series. This needed a > couple of fixes for build errors. > > (I'm always unsure if Reviewed-by should be carried over or not if the fixes > are minor. I apologize in advance if carring it over was the wrong thing to do > in this case.) For minor fixes, usually we carry Rb tag over. It's fine. LGTM Best regards, Krzysztof
On 11/03/2022 11:42, Krzysztof Kozlowski wrote: > On 11/03/2022 10:45, Vincent Whitchurch wrote: >> Add support for the UART block on the ARTPEC-8 SoC. This is closely >> related to the variants used on the Exynos chips. The register layout >> is identical to Exynos850 et al but the fifo size is different (64 bytes >> in each direction for all instances). >> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> >> Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> >> --- >> >> Notes: >> v2: >> - Added Krzysztof's Reviewed-by. >> - Expanded commit message >> - Fixed fifo size >> - Rebased on top of Krzysztof's "minor fixes/cleanups" series. This needed a >> couple of fixes for build errors. >> >> (I'm always unsure if Reviewed-by should be carried over or not if the fixes >> are minor. I apologize in advance if carring it over was the wrong thing to do >> in this case.) > > For minor fixes, usually we carry Rb tag over. It's fine. > Hi Greg, Just one note for you - this depends now on my v3 patchset here: https://lore.kernel.org/all/20220308080919.152715-1-krzysztof.kozlowski@canonical.com/ Best regards, Krzysztof
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 0e5ccb25bdb1..bd46e35ded40 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -236,7 +236,7 @@ config SERIAL_CLPS711X_CONSOLE config SERIAL_SAMSUNG tristate "Samsung SoC serial support" - depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || ARCH_APPLE || COMPILE_TEST + depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || ARCH_APPLE || ARCH_ARTPEC || COMPILE_TEST select SERIAL_CORE help Support for the on-chip UARTs on the Samsung diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 74d466cc4152..7d011d3fa3a6 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2828,6 +2828,36 @@ static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = { #define S5L_SERIAL_DRV_DATA NULL #endif +#if defined(CONFIG_ARCH_ARTPEC) +static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = { + .info = { + .name = "Axis ARTPEC-8 UART", + .type = TYPE_S3C6400, + .port_type = PORT_S3C6400, + .fifosize = 64, + .has_divslot = 1, + .rx_fifomask = S5PV210_UFSTAT_RXMASK, + .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, + .rx_fifofull = S5PV210_UFSTAT_RXFULL, + .tx_fifofull = S5PV210_UFSTAT_TXFULL, + .tx_fifomask = S5PV210_UFSTAT_TXMASK, + .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, + .def_clk_sel = S3C2410_UCON_CLKSEL0, + .num_clks = 1, + .clksel_mask = 0, + .clksel_shift = 0, + }, + .def_cfg = { + .ucon = S5PV210_UCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + .has_fracval = 1, + } +}; +#define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data) +#else +#define ARTPEC8_SERIAL_DRV_DATA (NULL) +#endif + static const struct platform_device_id s3c24xx_serial_driver_ids[] = { { .name = "s3c2410-uart", @@ -2856,6 +2886,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = { }, { .name = "exynos850-uart", .driver_data = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA, + }, { + .name = "artpec8-uart", + .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, }, { }, }; @@ -2881,6 +2914,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { .data = S5L_SERIAL_DRV_DATA }, { .compatible = "samsung,exynos850-uart", .data = EXYNOS850_SERIAL_DRV_DATA }, + { .compatible = "axis,artpec8-uart", + .data = ARTPEC8_SERIAL_DRV_DATA }, {}, }; MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); @@ -3034,6 +3069,8 @@ OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart", s5pv210_early_console_setup); OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", s5pv210_early_console_setup); +OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart", + s5pv210_early_console_setup); /* Apple S5L */ static int __init apple_s5l_early_console_setup(struct earlycon_device *device,