| Message ID | 20220318103729.157574-31-Julia.Lawall@inria.fr (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 170a0c56c5ec597fa15447e63272827a80a19be1 |
| Headers | show |
| Series | ARM: s3c: fix typos in comments | expand |
On Fri, 18 Mar 2022 11:37:26 +0100, Julia Lawall wrote: > Various spelling mistakes in comments. > Detected with the help of Coccinelle. > > Applied, thanks! [1/1] ARM: s3c: fix typos in comments commit: 170a0c56c5ec597fa15447e63272827a80a19be1 Best regards,
diff --git a/arch/arm/mach-s3c/iotiming-s3c2410.c b/arch/arm/mach-s3c/iotiming-s3c2410.c index 28d9f473e24a..09f388d8f824 100644 --- a/arch/arm/mach-s3c/iotiming-s3c2410.c +++ b/arch/arm/mach-s3c/iotiming-s3c2410.c @@ -259,7 +259,7 @@ static const unsigned int tacc_tab[] = { /** * get_tacc - turn tACC value into cycle time * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds. - * @val: The bank timing register value, shifed down. + * @val: The bank timing register value, shifted down. */ static unsigned int get_tacc(unsigned long hclk_tns, unsigned long val) diff --git a/arch/arm/mach-s3c/pm-s3c64xx.c b/arch/arm/mach-s3c/pm-s3c64xx.c index 4f1778123dee..2529f21736ff 100644 --- a/arch/arm/mach-s3c/pm-s3c64xx.c +++ b/arch/arm/mach-s3c/pm-s3c64xx.c @@ -323,7 +323,7 @@ void s3c_pm_arch_update_uart(void __iomem *regs, struct pm_uart_save *save) /* S3C64XX UART blocks only support level interrupts, so ensure that * when we restore unused UART blocks we force the level interrupt - * settigs. */ + * settings. */ save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; /* We have a constraint on changing the clock type of the UART
Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> --- arch/arm/mach-s3c/iotiming-s3c2410.c | 2 +- arch/arm/mach-s3c/pm-s3c64xx.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)