| Message ID | 20220407074432.424578-2-vincent.whitchurch@axis.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 99b701fd2758d046d9e6ecdef1a3320d29b8b1d9 |
| Headers | show |
| Series | clocksource: Add MCT support for ARTPEC-8 | expand |
On Thu, Apr 07, 2022 at 09:44:29AM +0200, Vincent Whitchurch wrote: > The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts. > > The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which > share one MCT with one global and eight local timers. The Cortex-A53 > and Cortex-A5 do not have cache-coherency between them, and therefore > run two separate kernels. > > The Cortex-A53 boots first and starts the global free-running counter > and also registers a clock events device using the global timer. (This > global timer clock events is usually replaced by arch timer clock events > for each of the cores.) > > When the A5 boots (via the A53), it should not use the global timer > interrupts or write to the global timer registers. This is because even > if there are four global comparators, the control bits for all four are > in the same registers, and we would need to synchronize between the > cpus. Instead, the global timer FRC (already started by the A53) should > be used as the clock source, and one of the local timers which are not > used by the A53 can be used for clock events on the A5. > > To support this hardware, add a compatible for the MCT as well as two > new properties to describe the hardware-mandated sharing of the FRC and > dedicating local timers to specific processors. > > Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> > --- > > Notes: > v3: > - Add all required bindings for ARTPEC-8 in one patch > - Rename and split local-timer-only to samsung,local-timers and > samsung,frc-shared > - Restrict above properties to the ARTPEC-8 compatible. > - Rewrite descriptions of properties to hopefully describe hardware. > > v2: > - Use devicetree property instead of module parameter. > > .../timer/samsung,exynos4210-mct.yaml | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) What's this based on? Doesn't apply on v5.18-rc1. Rob
On Thu, Apr 07, 2022 at 05:04:09PM +0200, Rob Herring wrote: > On Thu, Apr 07, 2022 at 09:44:29AM +0200, Vincent Whitchurch wrote: > > .../timer/samsung,exynos4210-mct.yaml | 26 +++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > What's this based on? Doesn't apply on v5.18-rc1. This series is still based on Krzysztof's "dt-bindings: timer: exynos4210-mct: describe known hardware and its interrupts". The cover letter mentions this but not very prominently, sorry. That patch was reviewed a while ago but doesn't seem to have made it to v5.18-rc1, but I see that Krzysztof reposted it yesterday: https://lore.kernel.org/lkml/20220407194127.19004-1-krzysztof.kozlowski@linaro.org/
On 07/04/2022 09:44, Vincent Whitchurch wrote: > The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts. > > The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which > share one MCT with one global and eight local timers. The Cortex-A53 > and Cortex-A5 do not have cache-coherency between them, and therefore > run two separate kernels. > > The Cortex-A53 boots first and starts the global free-running counter > and also registers a clock events device using the global timer. (This > global timer clock events is usually replaced by arch timer clock events > for each of the cores.) > > When the A5 boots (via the A53), it should not use the global timer > interrupts or write to the global timer registers. This is because even > if there are four global comparators, the control bits for all four are > in the same registers, and we would need to synchronize between the > cpus. Instead, the global timer FRC (already started by the A53) should > be used as the clock source, and one of the local timers which are not > used by the A53 can be used for clock events on the A5. > > To support this hardware, add a compatible for the MCT as well as two > new properties to describe the hardware-mandated sharing of the FRC and > dedicating local timers to specific processors. > > Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> > --- > This is rebased on my patch: https://lore.kernel.org/lkml/20220407194127.19004-1-krzysztof.kozlowski@linaro.org/ Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 1584944c7ac4..bcfc849ca087 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -25,6 +25,7 @@ properties: - samsung,exynos4412-mct - items: - enum: + - axis,artpec8-mct - samsung,exynos3250-mct - samsung,exynos5250-mct - samsung,exynos5260-mct @@ -46,6 +47,19 @@ properties: reg: maxItems: 1 + samsung,frc-shared: + type: boolean + description: | + Indicates that the hardware requires that this processor share the + free-running counter with a different (main) processor. + + samsung,local-timers: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16 + description: | + List of indices of local timers usable from this processor. + interrupts: description: | Interrupts should be put in specific order. This is, the local timer @@ -75,6 +89,17 @@ required: - reg allOf: + - if: + not: + properties: + compatible: + contains: + enum: + - axis,artpec8-mct + then: + properties: + samsung,local-timers: false + samsung,frc-shared: false - if: properties: compatible: @@ -102,6 +127,7 @@ allOf: compatible: contains: enum: + - axis,artpec8-mct - samsung,exynos5260-mct - samsung,exynos5420-mct - samsung,exynos5433-mct
The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts. The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and therefore run two separate kernels. The Cortex-A53 boots first and starts the global free-running counter and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots (via the A53), it should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this hardware, add a compatible for the MCT as well as two new properties to describe the hardware-mandated sharing of the FRC and dedicating local timers to specific processors. Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> --- Notes: v3: - Add all required bindings for ARTPEC-8 in one patch - Rename and split local-timer-only to samsung,local-timers and samsung,frc-shared - Restrict above properties to the ARTPEC-8 compatible. - Rewrite descriptions of properties to hopefully describe hardware. v2: - Use devicetree property instead of module parameter. .../timer/samsung,exynos4210-mct.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+)