From patchwork Wed May 4 11:40:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 12837746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D25A2C433EF for ; Wed, 4 May 2022 11:41:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348921AbiEDLpB (ORCPT ); Wed, 4 May 2022 07:45:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348917AbiEDLpB (ORCPT ); Wed, 4 May 2022 07:45:01 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90ADFE0D2 for ; Wed, 4 May 2022 04:41:25 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id j8-20020a17090a060800b001cd4fb60dccso1020449pjj.2 for ; Wed, 04 May 2022 04:41:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pnxPwikYcR/jRiJl0SfLW9jDFUFDEElKVltkxR/q3qU=; b=rMeI6li5cSb5bfYuFxYii7uXpogq73tD95HMSXX3ah4VSllZwn/xt036BLc1+TUI6f jbVkxmIsx3s6srnnnbK135jj0jJ9vroya9ZIEYfn4NWqeEy/D7cpN1IL6O6lzXZaIbn2 CDKSZSsAFWO9n3pLwogdozlLBBPn/gPlTzZ9I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pnxPwikYcR/jRiJl0SfLW9jDFUFDEElKVltkxR/q3qU=; b=2b3vsJ3WjcdOjepLKbCdpJJfUPpc5FEHZv/G60AaNC50/XI17QnkxgcTWjcHiu3Ay4 iq3vPLf3and2HLtQqHQx6oGWS8ATwfh48sl4x3w9vwMOMRG6LyCsbCKSYaKG9MUOzr1u 6X/2jrYxeCq5GRJEUSQhM2vtHR2H+YCQdYCroNnf7MYeHyE/5NWPBl0lMtmLqQuvjDMc Nq5wihGnFDL3+ixHoX91rI7MVZUp9SXCp52eDkL2xUsJOwRq5o4+lYnh8ZT4Y3d4ehb2 mb0WUQjqFJEbl4ABoFxoMXZG7eUiM5zhfK3YzbWU+IGJhxtItbKMlNLybAe3X+gc9Bm1 Qt+A== X-Gm-Message-State: AOAM532pazyFgXdJG6BFdkj5LQ9y+a2h5mck6qzCmsrbRNudxVP2+Slx jEExi5/rq5gSknmiYkUzDTlHHA== X-Google-Smtp-Source: ABdhPJwC3qfBwE1O4Eo41xPVk7grFlNFz3ubLdcJAaZ4//IGYIF9K66D9EFDJIo7sUUwQBT7EdCDNQ== X-Received: by 2002:a17:90a:7acb:b0:1d9:85a5:e1e3 with SMTP id b11-20020a17090a7acb00b001d985a5e1e3mr9731041pjl.172.1651664485044; Wed, 04 May 2022 04:41:25 -0700 (PDT) Received: from localhost.localdomain ([183.83.137.38]) by smtp.gmail.com with ESMTPSA id k15-20020aa790cf000000b0050dc7628174sm8027498pfk.78.2022.05.04.04.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 04:41:24 -0700 (PDT) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Fancy Fang , Tim Harvey , Michael Nazzareno Trimarchi , Adam Ford , Neil Armstrong , Robert Foss , Laurent Pinchart , Tommaso Merciai Cc: Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP Linux Team , linux-amarula , Jagan Teki Subject: [PATCH v2 06/12] drm: bridge: samsung-dsim: Fix PLL_P (PMS_P) offset Date: Wed, 4 May 2022 17:10:15 +0530 Message-Id: <20220504114021.33265-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220504114021.33265-1-jagan@amarulasolutions.com> References: <20220504114021.33265-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020 with 13.7.10.1 Master PLL PMS Value setting Register mentioned PMS_P offset range from BIT[18-13] and the upstream driver is using the same offset. However, offset 13 is not working on i.MX8M Mini platforms but downstream NXP driver is using 14 [1] and it is working with i.MX8M Mini SoC. Not sure about whether it is reference manual documentation or something else but this patch trusts the downstream code and fixes the PLL_P offset. [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211 v2: * none v1: * updated commit message * add downstream driver link Signed-off-by: Frieder Schrempf Signed-off-by: Jagan Teki --- drivers/gpu/drm/bridge/samsung-dsim.c | 10 ++++++++-- include/drm/bridge/samsung-dsim.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index b9361af5ef2d..8f9ae16d45bc 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -169,7 +169,7 @@ /* DSIM_PLLCTRL */ #define DSIM_FREQ_BAND(x) ((x) << 24) #define DSIM_PLL_EN (1 << 23) -#define DSIM_PLL_P(x) ((x) << 13) +#define DSIM_PLL_P(x, offset) ((x) << (offset)) #define DSIM_PLL_M(x) ((x) << 4) #define DSIM_PLL_S(x) ((x) << 1) @@ -369,6 +369,7 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, .platform_init = true, }; @@ -382,6 +383,7 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, .platform_init = true, }; @@ -393,6 +395,7 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, .platform_init = true, }; @@ -405,6 +408,7 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 0, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5433_reg_values, .platform_init = true, }; @@ -417,6 +421,7 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 1, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5422_reg_values, .platform_init = true, }; @@ -564,7 +569,8 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, writel(driver_data->reg_values[PLL_TIMER], dsi->reg_base + driver_data->plltmr_reg); - reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); + reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | + DSIM_PLL_M(m) | DSIM_PLL_S(s); if (driver_data->has_freqband) { static const unsigned long freq_bands[] = { diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h index 70224d20414b..e5291e105227 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -40,6 +40,7 @@ struct samsung_dsim_driver_data { unsigned int max_freq; unsigned int wait_for_reset; unsigned int num_bits_resol; + unsigned int pll_p_offset; const unsigned int *reg_values; bool platform_init; };