| Message ID | 20220628104138.152118-3-chanho61.park@samsung.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 6ac24a3a24a9e88f5e1ee8e96fd9d39fcab28b3f |
| Headers | show |
| Series | [v2,1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 | expand |
On 28/06/2022 12:41, Chanho Park wrote: > "gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0 > and peric1 respectively. > > Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 22. 6. 28. 19:41, Chanho Park wrote: > "gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0 > and peric1 respectively. > > Signed-off-by: Chanho Park <chanho61.park@samsung.com> > --- > drivers/clk/samsung/clk-exynosautov9.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c > index d9e1f8e4a7b4..c5a4e1bee711 100644 > --- a/drivers/clk/samsung/clk-exynosautov9.c > +++ b/drivers/clk/samsung/clk-exynosautov9.c > @@ -1330,6 +1330,10 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { > "mout_peric0_bus_user", > CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, > 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_PCLK_1, "gout_peric0_pclk_1", > + "mout_peric0_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, > + 21, 0, 0), > GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2", > "mout_peric0_bus_user", > CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, > @@ -1581,6 +1585,10 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { > "mout_peric1_bus_user", > CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0, > 21, 0, 0), > + GATE(CLK_GOUT_PERIC1_PCLK_1, "gout_peric1_pclk_1", > + "mout_peric1_bus_user", > + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, > + 21, 0, 0), > GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2", > "mout_peric1_bus_user", > CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c index d9e1f8e4a7b4..c5a4e1bee711 100644 --- a/drivers/clk/samsung/clk-exynosautov9.c +++ b/drivers/clk/samsung/clk-exynosautov9.c @@ -1330,6 +1330,10 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PCLK_1, "gout_peric0_pclk_1", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, @@ -1581,6 +1585,10 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { "mout_peric1_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0, 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PCLK_1, "gout_peric1_pclk_1", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, + 21, 0, 0), GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2", "mout_peric1_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
"gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0 and peric1 respectively. Signed-off-by: Chanho Park <chanho61.park@samsung.com> --- drivers/clk/samsung/clk-exynosautov9.c | 8 ++++++++ 1 file changed, 8 insertions(+)