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Wed, 27 Jul 2022 15:06:12 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas2p3.samsung.com (KnoxPortal) with ESMTPA id 20220727060612epcas2p355e7f9ca3700cad4778e944cbdbf2d50~Fmo4GIq8a1065410654epcas2p35; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220727060612epsmtrp2afb298f10c3de36e2af79f2c4e5d3bfa~Fmo4EPVt72781327813epsmtrp2z; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) X-AuditID: b6c32a47-5f7ff700000025aa-c3-62e0d5d4f2d2 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 41.50.08802.4D5D0E26; Wed, 27 Jul 2022 15:06:12 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220727060612epsmtip192d252485799370b0828d5fb9f19fdea~Fmo32WL6B2680226802epsmtip1S; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) From: Chanho Park To: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Krzysztof Kozlowski , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski Cc: Sam Protsenko , Alim Akhtar , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH 1/6] dt-bindings: clk: exynosautov9: add fys0 clock definitions Date: Wed, 27 Jul 2022 15:01:41 +0900 Message-Id: <20220727060146.9228-2-chanho61.park@samsung.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220727060146.9228-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrDJsWRmVeSWpSXmKPExsWy7bCmqe6Vqw+SDM48M7d4MG8bm8Xl/doW 1788Z7WYf+Qcq0Xfi4fMFntfb2W32PT4GqvFx557rBYzzu9jsrh4ytWide8RdovDb9pZLf5d 28hi8bwPKL5q1x9GB36P9zda2T12zrrL7rFpVSebx51re9g8Ni+p9+jbsorR4/MmuQD2qGyb jNTElNQihdS85PyUzLx0WyXv4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfMHKCrlRTKEnNK gUIBicXFSvp2NkX5pSWpChn5xSW2SqkFKTkF5gV6xYm5xaV56Xp5qSVWhgYGRqZAhQnZGauX z2Qq+C5ccXbfIsYGxpeCXYycHBICJhKrTz9m62Lk4hAS2MEocW7eGyYI5xOjxK4l65ghnM+M Ev2NU9lhWr6cfscOkdjFKPFiZQ9YQkjgI6PEo3d6IDabgK7EluevGEGKRAQeM0kcPtIGtoRZ oI1JYtqzjawgVcICgRI/H59gA7FZBFQlvhxqYQGxeQVsJfre7meBWCcvcf1mGzOIzSlgJ7Fj zU4miBpBiZMzn4DVMAPVNG+dDXarhMBaDolTp7ZBNbtIbFt3mxnCFpZ4dXwL1A9SEp/f7WWD sIslls76xATR3MAocXnbL6iEscSsZ+1AP3AAbdCUWL9LH8SUEFCWOHILai+fRMfhv+wQYV6J jjYhiEZ1iQPbp0NdICvRPeczK4TtIdH2aSULJLAmMkpMehk4gVFhFpJvZiH5ZhbC3gWMzKsY xVILinPTU4uNCozhUZycn7uJEZyMtdx3MM54+0HvECMTB+MhRgkOZiUR3oTo+0lCvCmJlVWp RfnxRaU5qcWHGE2BYT2RWUo0OR+YD/JK4g1NLA1MzMwMzY1MDcyVxHm9UjYkCgmkJ5akZqem FqQWwfQxcXBKNTCJ2wa/N2CQjn85/a/uszKJhIAmeYuu2q2zX5rYbVV6NYd/45of3PdWdzt9 PsN1kJeJeUniJL7DS5V0pm77+qvsVlmHhuWWSV6h1aXObq9LyyS/Bv69HeQp9NyuYIqA7vNS cffHBxyTxNn3q/3/L168dZNtYfW+10J5DoEa+RNTz67k8+laxiWdvKMte/n05erys4qlPHJl XrOe+7hjlaLFAfNcp98qSaffvtvVuoFn7o7gjLW8Nqfz5nlGh0w6vdLR7cLF8nescqlPFHbb uHj67j+v9ta8aW7Lrxl8fU+LDTwbIp4/vC1R+tgmLVRrQ5Sy2DoLP8NzvexPPkv7X2U+nBlk dGgy5ytdPqGCp0osxRmJhlrMRcWJAH670P9PBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRmVeSWpSXmKPExsWy7bCSnO6Vqw+SDOb8F7d4MG8bm8Xl/doW 1788Z7WYf+Qcq0Xfi4fMFntfb2W32PT4GqvFx557rBYzzu9jsrh4ytWide8RdovDb9pZLf5d 28hi8bwPKL5q1x9GB36P9zda2T12zrrL7rFpVSebx51re9g8Ni+p9+jbsorR4/MmuQD2KC6b lNSczLLUIn27BK6M1ctnMhV8F644u28RYwPjS8EuRk4OCQETiS+n37F3MXJxCAnsYJT4+mQV M0RCVuLZux3sELawxP2WI6wQRe8ZJdZs3QRWxCagK7Hl+StGkISIwHMmiSkrDoI5zAJdTBJ3 2j6BtQsL+EtsPP+IDcRmEVCV+HKohQXE5hWwleh7u58FYoW8xPWbbWBTOQXsJHas2ckEYgsB 1cx81QRVLyhxcuYTMJsZqL5562zmCYwCs5CkZiFJLWBkWsUomVpQnJueW2xYYJSXWq5XnJhb XJqXrpecn7uJERw5Wlo7GPes+qB3iJGJg/EQowQHs5IIb0L0/SQh3pTEyqrUovz4otKc1OJD jNIcLErivBe6TsYLCaQnlqRmp6YWpBbBZJk4OKUamOxnKOy1ZL/dKl30NVTUqfSzAeuKeQe6 5sQk2P/8JZ+qdfZj2tfVghf288ftKVbw1P+u9vTqioPff+habl128WZJtbVyQlWzy4aLN7YI Fz6ZFX3bM1ro6V/3TAX998F2S0zVJ8/8u2NrzNwVWi+NnVyu3dFat2mjspbuQpuCc3wWTyYL GTgVMzJ3zWie2cBxXPtu9NdnLQ5c7wREdcRM8gNn21nmXf6/wdTg9tEvLF9P2/OZB5fzxDE7 Bx6uvavTeidpgbTxvW8LnBf/7n8kdOLvzWPz734rr5v5yqr5/Y31c2awiaU5u/gan30ac3nG 5R/S61NPBypdbRHMk55/qai2+tf8lYzqbUKT13xv8FViKc5INNRiLipOBAD7+/LgCwMAAA== X-CMS-MailID: 20220727060612epcas2p355e7f9ca3700cad4778e944cbdbf2d50 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220727060612epcas2p355e7f9ca3700cad4778e944cbdbf2d50 References: <20220727060146.9228-1-chanho61.park@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add fsys0(for PCIe) clock definitions. Signed-off-by: Chanho Park Acked-by: Chanwoo Choi Acked-by: Krzysztof Kozlowski --- .../dt-bindings/clock/samsung,exynosautov9.h | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h index ea9f91b4eb1a..6305a84396ce 100644 --- a/include/dt-bindings/clock/samsung,exynosautov9.h +++ b/include/dt-bindings/clock/samsung,exynosautov9.h @@ -185,6 +185,49 @@ #define CORE_NR_CLK 6 +/* CMU_FSYS0 */ +#define CLK_MOUT_FSYS0_BUS_USER 1 +#define CLK_MOUT_FSYS0_PCIE_USER 2 +#define CLK_GOUT_FSYS0_BUS_PCLK 3 + +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK 4 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK 5 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK 6 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK 7 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK 8 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK 9 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK 10 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK 11 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_PIPE_CLK 12 +#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK 13 +#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK 14 + +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK 15 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK 16 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK 17 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK 18 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK 19 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK 20 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK 21 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK 22 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_PIPE_CLK 23 +#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK 24 +#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK 25 + +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK 26 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK 27 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK 28 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK 29 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK 30 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK 31 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK 32 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK 33 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_PIPE_CLK 34 +#define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35 +#define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36 + +#define FSYS0_NR_CLK 37 + /* CMU_FSYS2 */ #define CLK_MOUT_FSYS2_BUS_USER 1 #define CLK_MOUT_FSYS2_UFS_EMBD_USER 2