| Message ID | 20221129115531.102932-3-sriranjani.p@samsung.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v4,1/2] dt-bindings: soc: samsung: exynos-sysreg: Add tesla FSD sysreg compatibles | expand |
>-----Original Message----- >From: Sriranjani P [mailto:sriranjani.p@samsung.com] >Sent: 29 November 2022 17:26 >To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; >devicetree@vger.kernel.org; alim.akhtar@samsung.com; >pankaj.dubey@samsung.com; ravi.patel@samsung.com; >sathya@samsung.com >Cc: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux- >samsung-soc@vger.kernel.org; Sriranjani P <sriranjani.p@samsung.com> >Subject: [PATCH v4 2/2] arm64: dts: fsd: add sysreg device node > >Add SYSREG controller device node, which is available in PERIC, FSYS0, >FSYS1 and CAM block of FSD SoC. > >Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> >Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> >Signed-off-by: Sriranjani P <sriranjani.p@samsung.com> >--- > arch/arm64/boot/dts/tesla/fsd.dtsi | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > >diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi >b/arch/arm64/boot/dts/tesla/fsd.dtsi >index f35bc5a288c2..ff625fb71fbe 100644 >--- a/arch/arm64/boot/dts/tesla/fsd.dtsi >+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi >@@ -466,6 +466,11 @@ > clock-names = "fin_pll"; > }; > >+ sysreg_cam: system-controller@12630000 { >+ compatible = "tesla,fsd-cam-sysreg", "syscon"; >+ reg = <0x0 0x12630000 0x0 0x500>; >+ }; >+ > clock_mfc: clock-controller@12810000 { > compatible = "tesla,fsd-clock-mfc"; > reg = <0x0 0x12810000 0x0 0x3000>; >@@ -492,6 +497,11 @@ > "dout_cmu_peric_shared1div4_dmaclk"; > }; > >+ sysreg_peric: system-controller@14030000 { >+ compatible = "tesla,fsd-peric-sysreg", "syscon"; >+ reg = <0x0 0x14030000 0x0 0x1000>; >+ }; >+ > clock_fsys0: clock-controller@15010000 { > compatible = "tesla,fsd-clock-fsys0"; > reg = <0x0 0x15010000 0x0 0x3000>; >@@ -506,6 +516,11 @@ > "dout_cmu_fsys0_shared0div4"; > }; > >+ sysreg_fsys0: system-controller@15030000 { >+ compatible = "tesla,fsd-fsys0-sysreg", "syscon"; >+ reg = <0x0 0x15030000 0x0 0x1000>; >+ }; >+ > clock_fsys1: clock-controller@16810000 { > compatible = "tesla,fsd-clock-fsys1"; > reg = <0x0 0x16810000 0x0 0x3000>; >@@ -518,6 +533,11 @@ > "dout_cmu_fsys1_shared0div4"; > }; > >+ sysreg_fsys1: system-controller@16830000 { >+ compatible = "tesla,fsd-fsys1-sysreg", "syscon"; >+ reg = <0x0 0x16830000 0x0 0x1000>; >+ }; >+ > mdma0: dma-controller@10100000 { > compatible = "arm,pl330", "arm,primecell"; > reg = <0x0 0x10100000 0x0 0x1000>; >-- >2.17.1 Reviewed-by: Ravi Patel <ravi.patel@samsung.com>
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index f35bc5a288c2..ff625fb71fbe 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -466,6 +466,11 @@ clock-names = "fin_pll"; }; + sysreg_cam: system-controller@12630000 { + compatible = "tesla,fsd-cam-sysreg", "syscon"; + reg = <0x0 0x12630000 0x0 0x500>; + }; + clock_mfc: clock-controller@12810000 { compatible = "tesla,fsd-clock-mfc"; reg = <0x0 0x12810000 0x0 0x3000>; @@ -492,6 +497,11 @@ "dout_cmu_peric_shared1div4_dmaclk"; }; + sysreg_peric: system-controller@14030000 { + compatible = "tesla,fsd-peric-sysreg", "syscon"; + reg = <0x0 0x14030000 0x0 0x1000>; + }; + clock_fsys0: clock-controller@15010000 { compatible = "tesla,fsd-clock-fsys0"; reg = <0x0 0x15010000 0x0 0x3000>; @@ -506,6 +516,11 @@ "dout_cmu_fsys0_shared0div4"; }; + sysreg_fsys0: system-controller@15030000 { + compatible = "tesla,fsd-fsys0-sysreg", "syscon"; + reg = <0x0 0x15030000 0x0 0x1000>; + }; + clock_fsys1: clock-controller@16810000 { compatible = "tesla,fsd-clock-fsys1"; reg = <0x0 0x16810000 0x0 0x3000>; @@ -518,6 +533,11 @@ "dout_cmu_fsys1_shared0div4"; }; + sysreg_fsys1: system-controller@16830000 { + compatible = "tesla,fsd-fsys1-sysreg", "syscon"; + reg = <0x0 0x16830000 0x0 0x1000>; + }; + mdma0: dma-controller@10100000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0x10100000 0x0 0x1000>;